Memory devices and methods of manufacturing thereof

ABSTRACT

A memory device includes a first transistor formed in a first region of a substrate. The first transistor includes a structure protruding from the substrate, and a first source/drain (S/D) structure coupled to a first end of the protruding structure. The memory device includes a second transistor formed in a second region of the substrate. The second transistor includes a number of first semiconductor layers that are vertically spaced apart from one another, a second S/D structure coupled to a first end of the first semiconductor layers; and a third S/D structure coupled to a second end of the first semiconductor layers. The first region and the second region are laterally separated from each other by an isolation structure.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. Pat. Application No.16/916,905, filed Jun. 30, 2020, which is incorporated by referenceherein in its entirety.

BACKGROUND

This disclosure relates generally to a semiconductor device, and in someembodiments, to a memory device including one non-gate-all-around (GAA)transistor and one or more GAA transistors.

Integrated circuits (ICs) sometimes include one-time-programmable (OTP)memories to provide non-volatile memory (NVM) in which data are not lostwhen the IC is powered off. One type of the OTP devices includesanti-fuse memories. The anti-fuse memories include a number of anti-fusememory cells (or bit cells), whose terminals are disconnected beforeprogramming, and are shorted (e.g., connected) after the programming.The anti-fuse memories may be based on metal-oxide-semiconductor (MOS)technology. For example, an anti-fuse memory cell may include aprogramming MOS transistor (or MOS capacitor) and at least one readingMOS transistor. A gate dielectric of the programming MOS transistor maybe broken down to cause the gate and the source or drain region of theprogramming MOS transistor to be interconnected. Depending on whetherthe gate dielectric of the programming MOS transistor is broken down,different data bits can be presented by the anti-fuse memory cellthrough reading a resultant current flowing through the programming MOStransistor and reading MOS transistor. The anti-fuse memories have theadvantageous features of reverse-engineering proofing, since theprogramming states of the anti-fuse cells cannot be determined throughreverse engineering.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates an example circuit diagram of a memory cell, inaccordance with some embodiments.

FIG. 2 illustrates an example circuit diagram of another memory cell, inaccordance with some embodiments.

FIG. 3 illustrates a perspective view of a memory device including amemory cell shown in FIG. 1 , in accordance with some embodiments.

FIG. 4 illustrates a perspective view of a memory device including amemory cell shown in FIG. 2 , in accordance with some embodiments.

FIGS. 5, 6, 7, 8, 9, and 10 illustrate various example layouts to formmemory devices, in accordance with some embodiments.

FIG. 11 illustrates a flow chart of an example method to define a firstactive region and a second active region for a memory device, inaccordance with some embodiments.

FIGS. 12, 13, 14, 15, and 16 illustrate cross-sectional views of thememory device, made by the method of FIG. 11 , at various fabricationstages, in accordance with some embodiments.

FIG. 17 illustrates a flow chart of another example method to define afirst active region and a second active region for the memory device, inaccordance with some embodiments.

FIG. 18 illustrates a flow chart of an example method to follow themethod of either FIG. 11 or FIG. 17 to make the memory device, inaccordance with some embodiments.

FIGS. 19A, 19B, 19C, 20, 21, 22, 23, 24, 25, 26, 27A, 27B, 27C, and 28illustrate cross-sectional views of the memory device, made by themethod of FIG. 18 , at various fabrication stages, in accordance withsome embodiments.

FIG. 29 illustrates a cross-sectional view of another embodiments of thememory device, made by the method of FIG. 18 , in accordance with someembodiments.

FIG. 30 illustrates a cross-sectional view of yet another embodiments ofthe memory device, made by the method of FIG. 18 , in accordance withsome embodiments.

FIG. 31 illustrates a cross-sectional view of yet another embodiments ofthe memory device, made by the method of FIG. 18 , in accordance withsome embodiments.

FIG. 32 illustrates a cross-sectional view of yet another embodiments ofthe memory device, made by the method of FIG. 18 , in accordance withsome embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature’s relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

In contemporary semiconductor device fabrication processes, a largenumber of semiconductor devices, such as silicon channel n-type fieldeffect transistors (nFETs) and silicon germanium channel p-type fieldeffect transistors (pFETs), are fabricated on a single wafer. Non-planartransistor device architectures, such as fin-based transistors(typically referred to as “FinFETs”), can provide increased devicedensity and increased performance over planar transistors. Some advancednon-planar transistor device architectures, such as nanosheet (ornanowire) transistors, can further increase the performance over theFinFETs. When compared to the FinFET where the channel is partiallywrapped (e.g., straddled) by a gate structure, the nanosheet transistor,in general, includes a gate structure that wraps around the fullperimeter of one or more nanosheets for improved control of channelcurrent flow. For example, in a FinFET and a nanosheet transistor withsimilar dimensions, the nanosheet transistor can present larger drivingcurrent (I_(on)), smaller subthreshold leakage current (I_(off)), etc.The transistor that has a gate structure fully wrapping around itschannel is typically referred to as a gate-all-around (GAA) transistor;and the transistor that has a gate structure partially wrapping aroundor overlaying its channel, which includes the FinFET and planartransistor, is typically referred to as a non-gate-all-around (non-GAA)transistor.

Given the relative performance of nanosheet transistors as compared toFinFETs, some existing memory devices have configured the correspondingmemory cells in the nanosheet transistor configuration. For example, ananti-fuse memory cell may include a programming transistor and a readingtransistor, each of which is configured as a GAA transistor. However, asthe GAA transistor generally has multiple distinct nanostructures (e.g.,nanosheets, nanowires), when programming the anti-fuse memory cell,there may be only a portion of the gate dielectric (e.g., coupling toone of the nanosheets) is broken down, which can disadvantageously causethe anti-fuse memory cell to have a high resistance and/or a widevariation of the breakdown voltage (V_(BD)). Thus, existing memory cellsthat have adopted the GAA configuration have not been entirelysatisfactory.

The present disclosure provides various embodiments of a memory cell. Insome embodiments, the disclosed memory cell includes an anti-fuse memorycell that includes a programming transistor and one or more readingtransistors. The programming transistor is configured as a non-GAAtransistor (e.g., a FinFET, a planar transistor), and the one or morereading transistors are each configured as a GAA transistor. The non-GAAtransistor and the one or more GAA transistors are separated from eachother over a substrate by at least one isolation structure (e.g., ashallow trench isolation (STI)). In other words, the non-GAA transistormay be formed in a first active region of the substrate, and the GAAtransistor(s) may be formed in a second active region, wherein the firstand second active regions are separated (e.g., electrically isolated)from each other by an STI. By configuring the programming transistor asa non-GAA transistor and each of the reading transistor(s) as a GAAtransistor, the memory cell, as disclosed herein, can have a morecontrollable breakdown voltage (e.g., a narrower variation of thebreakdown voltage), while maintaining the performance of the GAAtransistor after the memory cell is programmed.

FIG. 1 illustrates an example circuit diagram of a memory cell 100, inaccordance with some embodiments. As shown, the memory cell (orsometimes referred to as a memory bit cell, a memory bit, or a bit) 100includes a first transistor 110 and a second transistor 120. Each of thefirst and second transistors, 110 and 120, may include an n-typemetal-oxide-semiconductor field-effect-transistor (MOSFET). Thetransistors 110 and 120 may each include another type of the MOSFET,e.g., a p-type MOSFET. In some other embodiments, at least one of thetransistor 110 or 120 may be replaced by another type of electronicdevices, e.g., a MOS capacitor, while remaining within the scope of thepresent disclosure. The first transistor 110 and the second transistor120 are electrically coupled to each other in series. For example, drainof the first transistor, 110D, is connected to source of the secondtransistor, 120S.

The memory cell 100 may be configured as an one-time-programmable (OTP)memory cell such as, for example, an anti-fuse cell. It is understoodthat the memory cell 100 may be configured as any type of the memorycell that includes two transistors electrically coupled to each other inseries (e.g., a NOR-type non-volatile memory cell, a dynamicrandom-access memory (DRAM) cell, a two-transistor static random-accessmemory (SRAM) cell, etc.).

When the memory cell 100 is configured as an anti-fuse cell, the firsttransistor 110 can function as a programming transistor and the secondtransistor 120 can function as a reading transistor. As such, source ofthe first transistor 110S is floating (e.g., coupled to nothing), andgate of the first transistor 110G is coupled to a programming word line(WLP) 130; and gate of the second transistor 120G is coupled to areading word line (WLR) 132, and drain of the second transistor 120D iscoupled to a bit line (BL) 134.

To program the memory cell 100, the reading transistor 120 is turned onby supplying a voltage (e.g., a positive voltage corresponding to alogic high state) to the gate 120G via the WLR 132. Prior to,concurrently with or subsequently to the reading transistor 120 beingturned on, a sufficiently high voltage (e.g., a breakdown voltage(V_(BD))) is applied to the WLP 130, and a low voltage (e.g., a positivevoltage corresponding to a logic low state) is applied to the BL 134.The low voltage (applied on the BL 134) can be passed to the source 110Dsuch that V_(BD) will be created across the drain 110D and the gate 110Gto cause a breakdown of a portion of a gate dielectric (e.g., theportion between the drain 110D and the gate 110G) of the programmingtransistor 110. After the gate dielectric of the programming transistor110 is broken down, a behavior of the portion interconnecting the gate110G and drain 110D is equivalently resistive. For example, such aportion may function as a resistor 136, as symbolically shown in FIG. 1. Before the programming (before the gate dielectric of the programmingtransistor 110 is broken down), when the reading transistor 120 isturned on, no conduction path exists between the BL 134 and the WLP 130;and after the programming, when the reading transistor 120 is turned on,a conduction path exists between the BL 134 and the WLP 130 (e.g., viathe resistor 136).

To read the memory cell 100, similarly to the programming operation, thereading transistor 120 is turned on and the BL 134 is coupled to avoltage corresponding to the logic low state. In response, a positivevoltage is applied to the gate of the programming transistor 110G. Asdiscussed above, if the gate dielectric of the programming transistor110 is not broken down, no conduction path exists between the BL 134 andthe WLP 130. Thus, a relatively low current conducts from the WLP 130,through the transistors 110 and 120, and to the BL 134. If the gatedielectric of the programming transistor 110 is broken down, aconduction path exists between the BL 134 and the WLP 130. Thus, arelatively high current conducts from the WLP 130, through thetransistor 110 (now equivalent to the resistor 136) and transistor 120,and to the BL 134. Such a low current and high current may sometimes bereferred to as I_(off) and I_(on) of the memory cell 110, respectively.A circuit component (e.g., a sensing amplifier), coupled to the BL 134can differentiate I_(off) from I_(on) (or vice versa), and thusdetermine whether the memory cell 100 presents a logic high (“1”) or alogic low (“0”). For example, when I_(on) is read, the memory cell 100may present 1; and when I_(off) is read, the memory cell 100 may present0.

FIG. 2 illustrates an example circuit diagram of another memory cell200, in accordance with some embodiments. The memory cell 200 is similaras the memory cell 100 of FIG. 1 , except that the memory cell 200includes an additional reading transistor. As shown, the memory cell 200includes a first transistor 210, a second transistor 220, and a thirdtransistor 230. Each of the first, second, and third transistors,210-230, may include an n-type MOSFET. In some other embodiments, eachof the transistors 210-230 may include a p-type MOSFET while remainingwithin the scope of the present disclosure. The first transistor 210,the second transistor 220, and the third transistor 230 are electricallycoupled to each other in series. For example, drain of the firsttransistor, 210D, is connected to source of the second transistor, 220S,and drain of the second transistor, 220D, is connected to source of thethird transistor, 230S. The memory cell 200 may function as an anti-fusecell (as discussed above), where the first transistor 210 functions as aprogramming transistor of the anti-fuse cell and the second and thirdtransistors, 220 and 230, collectively function as reading transistorsof the anti-fuse cell. Similarly to the memory cell 100, gate of theprogramming transistor 210G is coupled to a WLP 240, the gates of thereading transistors, 220G and 230G, are respectively coupled to a WLR1242 and WLR2 244, and drain of the reading transistor 230D is coupled toa BL 250. Operations of the memory cell 200 is substantially similar tothe operations of the memory cell 100, and thus, the discussion will notbe repeated.

Referring to FIG. 3 , a perspective view of an example memory device 300is shown. In accordance with some embodiments, the memory device 300 maybe a portion of an anti-fuse memory cell that includes one programmingtransistor and one reading transistor, e.g., the memory cell 100 of FIG.1 . The perspective view of FIG. 3 is an overview of the anti-fusememory cell and thus, some of the features of the anti-fuse memory cellmay not be identified in FIG. 3 . More detailed features of the memorydevice 300 (or a memory device similar to 300) will be shown anddiscussed below with respect to the cross-sectional views of FIGS.19A-29 and 32 .

As shown in FIG. 3 , the memory device 300 includes a programmingtransistor 302 and a reading transistor 304. In some embodiments, theprogramming transistor 302 is configured as a non-GAA transistor (e.g.,a FinFET), and the reading transistor is configured as a GAA transistor(e.g., a nanosheet transistor). The programing transistor 302 and thereading transistor 304 may be formed on a semiconductor substrate 306 inrespective different active regions. For example, over a first activeregion 306A of the semiconductor substrate 306, the programmingtransistor 302 is formed; and over a second active region 306B of thesemiconductor substrate 306, the reading transistor 304 is formed,wherein the first and second active regions, 306A and 306B, arelaterally (e.g., along the X direction) separated from each other by anisolation structure (not shown in FIG. 3 ). Such an active region issometimes referred to as an oxide diffusion (OD) region.

Specifically, the programming transistor 302 includes a gate structure308 disposed over the active region 306A; and the reading transistor 304includes a gate structure 310 disposed over the active region 306B. Thegate structures 308 and 310, in parallel with each other, may beorientated and elongated along a lateral direction (e.g., the Ydirection). In the active region 306A, the programming transistor 302includes a source/drain structure 316 and a source/drain structure 318formed on respective sides of the gate structure 308. In the activeregion 306B, the reading transistor 310 includes a source/drainstructure 320 and a source/drain structure 322 formed on respectivesides of the gate structure 310.

The gate structure 308 is formed to straddle a structure 332 protrudingfrom the substrate 306 (hereinafter fin-based or protruding structure332), with the source/drain structures 316 and 318 coupled to itsrespective ends, e.g., along the X direction. The protruding structure332 can function as a channel of the programing transistor 302. The gatestructure 310 is formed to wrap around a number of nanostructures (e.g.,nanosheets, nanowires, or otherwise semiconductor layers with thedimensions of the order of a nanometer) 342 a, 342 b, and 342 c, withthe source/drain structures 320 and 322 coupled to their respectiveends, e.g., along the X direction. The semiconductor layers 342 a-c(which may sometimes be referred to as semiconductor layers 342) cancollectively function as a channel of the reading transistor 304. Theprotruding structure 332 and the semiconductor layers 342 a-c may beorientated and elongated along a lateral direction (e.g., the Xdirection), which is the same as the direction along which thesource/drain structures 316-322 are aligned with each other. As such,the active region 306A where the source/drain structures 316-318 and theprotruding structure 332 are formed, and the active region 306B wherethe source/drain structures 320-322 and the semiconductor layers 342 a-care formed, although laterally separated from each other, can be alignedwith each other along a lateral direction (e.g., the X direction).

Referring still to FIG. 3 , and in further detail, the gate structure310 can include multiple gate stacks, in some embodiments. Each of thegate stacks may include one or more gate dielectrics and one or moregate metals (not shown in FIG. 3 for clarity). Two of the gate stacksare configured to collectively wrap around a corresponding one of theone or more semiconductor layers 342 a-c. For instance, the gatestructure 310 includes gate stacks 310 a, 310 b, 310 c, and 310 d. Thegate stacks 310 a-d may have a width (along the Y direction)substantially similar as a width of the gate structure 310 (along the Ydirection), and the semiconductor layers 342 a-c are characterized witha width (along the Y direction) less than the width of the gate stacks310 a-d. Each of the gate stacks 310 a-d may further include portionsthat extend along the Z direction to be in contact with an adjacent gatestack. As such, two adjacent ones of the gate stacks 310 a-d can wrapthe full perimeter of a corresponding one of the semiconductor layers342 a-c.

For example, the gate stacks 310 a and 310 b can collectively wraparound at least four sides of the semiconductor layer 342 a, with twosides (or ends) of the semiconductor layer 342 a respectively coupled tothe source/drain structure 320 and source/drain structure 322; the gatestacks 310 b and 310 c can collectively wrap around at least four sidesof the semiconductor layer 342 b, with two sides (or ends) of thesemiconductor layer 342 b respectively coupled to the source/drainstructure 320 and source/drain structure 322; and the gate stacks 310 cand 310 d can collectively wrap around at least four sides of thesemiconductor layer 342 c, with two sides (or ends) of the semiconductorlayer 342 c respectively coupled to the source/drain structure 320 andsource/drain structure 322.

Referring to FIG. 4 , a perspective view of an example memory device 400is shown. In accordance with some embodiments, the memory device 400 maybe a portion of an anti-fuse memory cell that includes one programmingtransistor and two reading transistors, e.g., the memory cell 200 ofFIG. 2 . The perspective view of FIG. 4 is an overview of the anti-fusememory cell and thus, some of the features of the anti-fuse memory cellmay not be identified in FIG. 4 . More detailed features of the memorydevice 400 (or a memory device similar to 400) will be shown anddiscussed below with respect to the cross-sectional views of FIGS. 30and 31 .

As shown in FIG. 4 , the memory device 400 includes a programmingtransistor 402, a first reading transistor 404, and a second readingtransistor 406. In some embodiments, the programming transistor 402 isconfigured as a non-GAA transistor (e.g., a FinFET), and the readingtransistors, 404 and 406, are each configured as a GAA transistor (e.g.,a nanosheet transistor). The programing transistor 402 and the readingtransistors 404-406 may be formed on a semiconductor substrate 408 inrespective different active regions. For example, over a first activeregion 408A of the semiconductor substrate 408, the programmingtransistor 402 is formed; and over a second active region 408B of thesemiconductor substrate 408, the reading transistors 404-406 are formed,wherein the first and second active regions, 408A and 408B, arelaterally (e.g., along the X direction) separated from each other by anisolation structure (not shown in FIG. 4 ). Such an active region issometimes referred to as an oxide diffusion (OD) region.

Specifically, the programming transistor 402 includes a gate structure410 disposed over the active region 408A; and the reading transistors404 and 406 respectively include gate structures 412 and 414 disposedover the active region 408B. The gate structure 410, 412, and 414, inparallel with each other, may be orientated and elongated along alateral direction (e.g., the Y direction). In the active region 408A,the programming transistor 402 includes a source/drain structure 416 anda source/drain structure 418 formed on respective sides of the gatestructure 410. In the active region 408B, the reading transistor 404includes a source/drain structure 420 and a source/drain structure 422formed on respective sides of the gate structure 412; and the readingtransistor 406 includes the source/drain structure 422 and asource/drain structure 424 formed on respective sides of the gatestructure 414. In the illustrated embodiment of FIG. 4 , the readingtransistors 404 and 406 may share the same source/drain structure 422.However, the reading transistors 404 and 406 may not share the samesource/drain structure, while remaining within the scope of the presentdisclosure.

The gate structure 410 is formed to straddle a structure 432 protrudingfrom the substrate 408 (hereinafter fin-based or protruding structure432), with the source/drain structures 416 and 418 coupled to itsrespective ends, e.g., along the X direction. The protruding structure432 can function as a channel of the programing transistor 402. The gatestructure 412 is formed to wrap around a number of nanostructures (e.g.,nanosheets, nanowires, or otherwise semiconductor layers with thedimensions of the order of a nanometer) 442 a, 442 b, and 442 c, withthe source/drain structures 420 and 422 coupled to their respectiveends, e.g., along the X direction. The semiconductor layers 442 a-c(which may sometimes be referred to as semiconductor layers 442) cancollectively function as a channel of the reading transistor 404. Thegate structure 414 is formed to wrap around a number of othernanostructures (e.g., semiconductor layers) 452 a, 452 b, and 452 c,with the source/drain structures 422 and 424 coupled to their respectiveends, e.g., along the X direction. The semiconductor layers 452 a-c(which may sometimes be referred to as semiconductor layers 452) cancollectively function as a channel of the reading transistor 406. Theprotruding structure 432 and the semiconductor layers 442 a-c and 452a-c may be orientated and elongated along a lateral direction (e.g., theX direction), which is the same as the direction along which thesource/drain structures 416-424 are aligned with each other. As such,the active region 408A where the source/drain structures 416-418 and theprotruding structure 432 are formed, and the active region 408B wherethe source/drain structures 420-424 and the semiconductor layers 442 a-cand 452 a-c are formed, although laterally separated from each other,can be aligned with each other along a lateral direction (e.g., the Xdirection).

Each of the gate structures 412 and 414 can include multiple gatestacks, in some embodiments. Each of the gate stacks may include one ormore gate dielectrics and one or more gate metals (not shown in FIG. 4for clarity). Two of the gate stacks are configured to collectively wraparound a corresponding one of the one or more semiconductor layers. Asthe gate structures 412 and 414 are similar as the gate structure 310discussed with respect to FIG. 3 , discussions of the gate structures412 and 414 will not be repeated.

FIGS. 5, 6, 7, and 8 illustrate various examples of design layouts tofabricate an anti-fuse cell, in accordance with some embodiments. Thelayouts of FIGS. 5 to 8 may each be used to fabricate an anti-fusememory cell having one programing transistor and one reading transistor,e.g., the memory cell 100 of FIG. 1 . Further, the programmingtransistor may be formed as a non-GAA transistor and the readingtransistor may be formed as a GAA transistor, in some embodiments. Forexample, the non-GAA programming transistor may be a FinFET and the GAAreading transistor may be a nanosheet transistor. However, it isunderstood that the layouts of FIGS. 5 to 8 may be used to fabricate anyof various other combinations of transistors. For example, the non-GAAprogramming transistor may be a planar transistor and the GAA readingtransistor may be a nanowire transistor. In another example, the non-GAAprogramming transistor may be a FinFET and the GAA reading transistormay be a nanowire transistor. In yet another example, the non-GAAprogramming transistor may be a FinFET and the GAA reading transistormay be a vertical transistor.

As a representative example, each of the layouts of FIGS. 5 to 8 isconfigured to fabricate an anti-fuse memory cell similar to the memorydevice 300 that includes a non-GAA programming transistor and a GAAreading transistor shown in FIG. 3 . Thus, the following discussions ofFIGS. 5 to 8 will be provided in conjunction with FIG. 3 . It isappreciated that the layouts shown in FIGS. 5 to 8 have been simplifiedfor illustration purposes. Thus, each of the layouts may include one ormore other features while remaining within the scope of the presentdisclosure.

Referring to FIG. 5 , a layout 500 is depicted, in accordance with someembodiments. The layout 500 includes a feature 501 that defines theboundary of an anti-fuse memory cell (hereinafter cell boundary 501).Over the cell boundary 501, the layout 500 includes various features,each of which corresponds to one or more patterning process (e.g., aphotolithography process) to make a physical device feature.

For example, the layout 500 includes active features, 502A and 502B, andgate features, 504 and 506. The active feature 502A, extending along theX direction, may be configured to define a first active region, e.g.,306A of FIG. 3 . The active feature 502B, extending along the Xdirection, may be configured to define a second active region, e.g.,306B of FIG. 3 . Hereinafter, the active features 502A and 502B maysometimes be referred to as active regions 502A(306A) and 502B(306B),respectively. The gate feature 504, extending along the Y direction, maybe configured to form a first gate structure, e.g., 308 of FIG. 3 . Thegate feature 506, extending along the Y direction, may be configured toform a second gate structure, e.g., 310 of FIG. 3 . Hereinafter, thegate features 504 and 506 may sometimes be referred to as gatestructures 504(308) and 506(310), respectively. In some embodiments, awidth, W₁, of the gate structure 504(308) (extending along the Xdirection) may be wider than a width, W₂, of the gate structure 506(310)(extending along the X direction), as shown in FIG. 5 . In some otherembodiments, the width, W₁, can be equal to the width, W₂.

Each of the gate features can travel across a corresponding one of theactive features to form one or more sub-active features on side(s) ofthe gate feature, which may be configured to form respectivesource/drain structure(s). For example in FIG. 5 , the gate feature 504travels across the active feature 502A to form sub-active features, 508and 510, which may be used to form source/drain structures, e.g., 316and 318 of FIG. 3 . The gate feature 506 travels across the activefeature 502B to form sub-active features, 512 and 514, which may be usedto form source/drain structures, e.g., 320 and 322 of FIG. 3 .Hereinafter, the sub-active features 508, 510, 512, and 514 maysometimes be referred to as source/drain structures 508(316), 510(318),512(320), and 514(322), respectively.

In some embodiments, the portion of the active region 502A(306A) that isoverlaid by the gate structure 504(308) is configured to form thechannel of a non-GAA transistor, e.g., the protruding structure 332 ofFIG. 3 . The portion of the active region 502B(306B) that is overlaid bythe gate structure 506(310) is configured to form the channel of a GAAtransistor, e.g., the semiconductor layers 342 a-c of FIG. 3 . As such,the non-GAA programming transistor 302 (FIG. 3 ) can be formed based onthe active feature 502A and the gate feature 504 of the layout 500; andthe GAA reading transistor 304 (FIG. 3 ) can be formed based on theactive feature 502B and the gate feature 506 of the layout 500.

Upon forming the non-GAA programming transistor 302 and the GAA readingtransistor 304, a number of interconnecting structures can be formed tooperate the programming transistor 302 and reading transistor 304. Forexample, the drain of the programming transistor 302 (e.g., source/drainstructure 510(318)) and the source of the reading transistor 304 (e.g.,source/drain structure 512(320)) are connected to each other by aninterconnecting structure; the gate of the programming transistor 302(e.g., gate structure 504(308)) and the gate of the reading transistor304 (e.g., gate structure 506(310)) may be connected to interconnectingstructures that functions as WLP (e.g., 130 of FIG. 1 ) and WLR (e.g.,132 of FIG. 1 ), respectively; and the drain of the reading transistor304 (e.g., source/drain structure 514(322)) may be connected to aninterconnecting structure that functions as a BL (e.g., 134 of FIG. 1 ).

As illustrated in the example of FIG. 5 , the layout 500 includes anumber of features to form such interconnecting structures (e.g., WLP,WLR, BL, etc.) and additional interconnecting structures to connect tothose interconnecting structures. For example, the layout 500 includesfeatures 520, 522, 524, and 526 extending along the Y direction. Thefeatures 520, 522, 524, and 526 are configured to form interconnectingstructures to connect to the source/drain structure 508(316), thesource/drain structure 510(318), the source/drain structure 512(320),and the source/drain structure 514(322), respectively. Suchinterconnecting structures connecting to the source/drain structures aresometimes referred to as MDs, which may be formed as slot or trenchstructures. Accordingly, the features 520, 522, 524, and 526 mayhereinafter referred to as MD 520, MD 522, MD 524, and MD 526,respectively.

The layout 500 further includes features 528, 530, and 532, that areconfigured to form interconnecting structures to connect to the MDs 522,524, and 526, respectively. Such interconnecting structures aresometimes referred to as VDs, which may be formed as via structures.Accordingly, the features 528, 530, and 532 may hereinafter referred toas VD 528, VD 530, and VD 532, respectively.

The layout 500 further includes features 534 and 536 both extendingalong the X direction. The feature 534 is configured to form aninterconnecting structure interconnecting the transistors 302 and 304together, which is hereinafter referred to as interconnecting structure534. For example, the source/drain structure 510(318) of the programmingtransistor 302 can connect to the to the source/drain structure 512(320)of the reading transistor 304, through the MD 522, VD 528, theinterconnecting structure 534, the VD 530, and the MD 524. The feature536 is configured to form an interconnecting structure functioning as aBL, which is hereinafter referred to as BL 536. The BL 536 can connectto the source/drain structure 514(322) of the reading transistor 304,through the VD 532 and the MD 526.

The layout 500 further includes features 538 and 540 both extendingalong the Y direction. The features 538 and 540 are configured to forminterconnecting structures functioning as a WLP and WLR, respectively,which are hereinafter referred to as WLP 538 and WLR 540. The WLP 538may connect to the gate structure 504(308) of the programming transistor302 through an interconnecting structure, sometimes referred to as a VG(not shown), and the WLR 540 may connect to the gate structure 506(310)of the reading transistor 304 through another VG (not shown). Such VGsmay be formed as via structures, in some embodiments.

In some embodiments, the MDs 520-526, VDs 528-532, and the non-shown VGsmay be disposed in a middle-end-of-line (MEOL) network. Theinterconnecting structure 534 and BL 536 may be disposed in a firstmetallization layer of a back-end-of-line (BEOL) network. The WLP 538and WLR 540 may be disposed in a second metallization layer of the BEOLnetwork. The second metallization layer can be disposed over the firstmetallization layer, and the first metallization layer can be disposedover the MEOL network.

Referring to FIG. 6 , a layout 600 is depicted, in accordance with someembodiments. The layout 600 is similar to the layout 500 except that thelayout 600 further includes features to form one or more dummy gatestructures. Thus, some of the reference numerals of FIG. 5 will bereused in the following discussions of FIG. 6 .

As shown, the layout 600 further includes features 602 and 604 bothextending along the Y direction. The features 602 and 604 are configuredto form dummy gate structures, which are hereinafter referred to asdummy gate structures, 602 and 604. In some embodiments, the dummy gatestructures 602-604 may be similar as the gate structures 308-310 of FIG.3 (e.g., extending along the Y direction) but may not travel across anyactive region. Accordingly, the dummy gate structures 602-604 will notbe adopted as an active gate structure to electrically control currentin a finished semiconductor device (e.g., the memory device 300 of FIG.3 ). As shown in FIG. 6 , the dummy gate structure 602 is disposed alongone of the sides of the cell boundary 501. The dummy gate structure 604is disposed between the active regions 502A(306A) and 502B(306B).

Referring to FIG. 7 , a layout 700 is depicted, in accordance with someembodiments. The layout 700 is similar to the layout 600 except that thelayout 700 further includes features to form one or more interconnectingstructures. Thus, some of the reference numerals of FIG. 6 will bereused in the following discussions of FIG. 7 .

As shown, the layout 700 further includes a feature 702 configured toform an interconnecting structure (e.g., a VD). Hereinafter, the feature702 may be referred to as VD 702. Similar to the VDs 528 and 530, the VD702 is configured to connect to a corresponding MD, e.g., 520. Thelayout 700 includes a feature 704 similar to the feature 534 except thatthe feature 704 is configured to form an interconnecting structureconnecting to the VD 702, in addition to the VDs, 528 and 530. In otherwords, the feature 704 may further extend across the gate structure504(308), e.g., along the X direction. Hereinafter, the feature 704 maysometimes be referred to as interconnecting structure 704. By formingthe interconnecting structure 704, the source/drain structure 508(316),which is connected to the MD 520, the source/drain structure 510(318),which is connected to the MD 522, and the source/drain structure512(320), which is connected to the MD 524, can be interconnected to oneanother.

Referring to FIG. 8 , a layout 800 is depicted, in accordance with someembodiments. The layout 800 is similar to the layout 600 except that thelayout 800 includes a feature to form an active region partiallyoverlaid by a corresponding gate structure. Thus, some of the referencenumerals of FIG. 6 will be reused in the following discussions of FIG. 8.

As shown, the layout 800 includes a feature 802A configured to form anactive region. Hereinafter, the feature 802A may sometimes be referredto as active region 802A. The active region 802A is similar as theactive region 502A(306A) shown in FIGS. 5-7 except that the activeregion 802A is partially overlaid by the gate structure 504(308).Specifically, the portion of the active region 802A overlaid by the gatestructure 504(308) is offset toward the active region 502B(306B), insome embodiments. As such, when using the layout 800 to form the memorydevice 300 in FIG. 3 , the memory device 300 does not have thesource/drain structure 316. Further, the protruding structure 332 formedby the portion of the active region 802A overlaid by the gate structure504(308) may have an additional sidewall that is also overlaid by thegate structure 504(308). This sidewall should have been coupled to thesource/drain structure 316. The programming transistor 302 that has onlyone source/drain structure (e.g., the source/drain structure 318)coupled to its channel (e.g., the protruding structure 332) maysometimes be referred to as a MOS (or MOSFET) capacitor.

FIGS. 9 and 10 illustrate various examples of design layouts tofabricate an anti-fuse cell, in accordance with some embodiments. Thelayouts of FIGS. 9 to 10 may each be used to fabricate an anti-fusememory cell having one programing transistor and two readingtransistors, e.g., the memory cell 200 of FIG. 2 . Further, theprogramming transistor may be formed as a non-GAA transistor and thereading transistors may each be formed as a GAA transistor, in someembodiments. For example, the non-GAA programming transistor may be aFinFET and the GAA reading transistors may each be a nanosheettransistor. However, it is understood that the layouts of FIGS. 9 to 10may be used to fabricate any of various other combinations oftransistors, while remaining within the scope of the present disclosure.

As a representative example, each of the layouts of FIGS. 9 to 10 isconfigured to fabricate an anti-fuse memory cell similar to the memorydevice 400 that includes a non-GAA programming transistor and two GAAreading transistors shown in FIG. 4 . Thus, the following discussions ofFIGS. 9 to 10 will be provided in conjunction with FIG. 4 . It isappreciated that the layouts shown in FIGS. 9 to 10 have been simplifiedfor illustration purposes. Thus, each of the layouts may include one ormore other features while remaining within the scope of the presentdisclosure.

Referring to FIG. 9 , a layout 900 is depicted, in accordance with someembodiments. The layout 900 includes a feature 901 that defines theboundary of an anti-fuse memory cell (hereinafter cell boundary 901).Over the cell boundary 901, the layout 900 includes various features,each of which corresponds to one or more patterning process (e.g., aphotolithography process) to make a physical device feature.

For example, the layout 900 includes active features, 902A and 902B, andgate features, 904, 906, and 908. The active feature 902A, extendingalong the X direction, may be configured to form a first active region,e.g., 408A of FIG. 4 . The active feature 902B, extending along the Xdirection, may be configured to form a second active region, e.g., 408Bof FIG. 4 . Hereinafter, the active features 902A and 902B may sometimesbe referred to as active regions 902A(408A) and 902B(408B),respectively. The gate feature 904, extending along the Y direction, maybe configured to form a first gate structure, e.g., 410 of FIG. 4 . Thegate feature 906, extending along the Y direction, may be configured toform a second gate structure, e.g., 412 of FIG. 4 . The gate feature908, extending along the Y direction, may be configured to form a thirdgate structure, e.g., 414 of FIG. 4 . Hereinafter, the gate features904, 906, and 908 may sometimes be referred to as gate structures904(410), 906(412), and 908(414), respectively. In some embodiments, awidth, W₃, of the gate structure 904(410) (extending along the Xdirection) may be wider than a width, W₄, of the gate structures906(412) and 908(414) (extending along the X direction), as shown inFIG. 9 . In some other embodiments, the width, W₃, can be equal to thewidth, W₄.

Each of the gate features can travel across a corresponding one of theactive features to form one or more sub-active features on side(s) ofthe gate feature, which may be configured to form respectivesource/drain structure(s). For example in FIG. 9 , the gate feature 904travels across the active feature 902A to form sub-active features, 910and 912, which may be used to form source/drain structures, e.g., 416and 418 of FIG. 4 . The gate features 906 and 908 respectively travelacross the active feature 902B to form sub-active features, 914, 916,and 918, which may be used to form source/drain structures, e.g., 420,422, and 424 of FIG. 4 , respectively. Hereinafter, the sub-activefeatures 910, 912, 914, 916, and 918 may sometimes be referred to assource/drain structures 910(416), 912(418), 914(420), 916(422), and918(424), respectively.

In some embodiments, the portion of the active region 902A(408A) that isoverlaid by the gate structure 904(410) is configured to form thechannel of a non-GAA transistor, e.g., the protruding structure 432 ofFIG. 4 . The portion of the active region 902B(408B) that is overlaid bythe gate structure 906(412) is configured to form the channel of a firstGAA transistor, e.g., the semiconductor layers 442 a-c of FIG. 4 . Theportion of the active region 902B(408B) that is overlaid by the gatestructure 908(414) is configured to form the channel of a second GAAtransistor, e.g., the semiconductor layers 452 a-c of FIG. 4 . As such,the non-GAA programming transistor 402 (FIG. 4 ) can be formed based onthe active feature 902A and the gate feature 904 of the layout 900; theGAA reading transistor 404 (FIG. 4 ) can be formed based on the activefeature 902B and the gate feature 906 of the layout 900; and the GAAreading transistor 406 (FIG. 4 ) can be formed based on the activefeature 902B and the gate feature 908 of the layout 900.

Upon forming the non-GAA programming transistor 402 and the GAA readingtransistors 404-406, a number of interconnecting structures can beformed to operate the programming transistor 402 and reading transistors404-406. For example, the drain of the programming transistor 402 (e.g.,source/drain structure 912(418)) and the source of the readingtransistor 404 (e.g., source/drain structure 914(420)) are connected toeach other by an interconnecting structure; the gate of the programmingtransistor 402 (e.g., gate structure 904(410)), the gate of the readingtransistor 404 (e.g., gate structure 906(412)), and the gate of thereading transistor 406 (e.g., gate structure 908(414)) may be connectedto interconnecting structures that functions as WLP (e.g., 240 of FIG. 2), WLR1 (e.g., 242 of FIG. 2 ), and WLR2 (e.g., 244 of FIG. 2 ),respectively; and the drain of the reading transistor 406 (e.g.,source/drain structure 918(424)) may be connected to an interconnectingstructure that functions as a BL (e.g., 250 of FIG. 2 ).

As illustrated in the example of FIG. 9 , the layout 900 includes anumber of features to form such interconnecting structures (e.g., WLP,WLR1, WLR2, BL, etc.) and additional interconnecting structures toconnect to those interconnecting structures. For example, the layout 900includes features 920, 922, 924, 926, and 928 extending along the Ydirection. The features 920, 922, 924, 926, and 928 are configured toform interconnecting structures to connect to the source/drain structure910(416), the source/drain structure 912(418), the source/drainstructure 914(420), the source/drain structure 916(422), and thesource/drain structure 918(424), respectively. Such interconnectingstructures connecting to the source/drain structures are sometimesreferred to as MDs. Accordingly, the features 920, 922, 924, 926, and928 may hereinafter referred to as MD 920, MD 922, MD 924, MD 926, andMD 928, respectively.

The layout 900 further includes features 930, 932, and 934, that areconfigured to form interconnecting structures to connect to the MDs 922,924, and 928, respectively. Such interconnecting structures aresometimes referred to as VDs. Accordingly, the features 930, 932, and934 may hereinafter referred to as VD 930, VD 932, and VD 934,respectively.

The layout 900 further includes features 940 and 942 both extendingalong the X direction. The feature 940 is configured to form aninterconnecting structure interconnecting the transistors 402 and 404together, which is hereinafter referred to as interconnecting structure940. For example, the source/drain structure 912(418) of the programmingtransistor 402 can connect to the to the source/drain structure 914(420)of the reading transistor 404, through the MD 922, VD 930, theinterconnecting structure 940, the VD 932, and the MD 924. The feature942 is configured to form an interconnecting structure functioning as aBL, which is hereinafter referred to as BL 942. The BL 942 can connectto the source/drain structure 918(424) of the reading transistor 406,through the VD 934 and the MD 928.

The layout 900 further includes features 944, 946, and 948 bothextending along the Y direction. The features 944, 946, and 948 areconfigured to form interconnecting structures functioning as a WLP,WLR1, and WLR2, respectively, which are hereinafter referred to as WLP944, WLR1 946 and WLR2 948. The WLP 944 may connect to the gatestructure 904(410) of the programming transistor 402 through aninterconnecting structure, sometimes referred to as a VG (not shown),the WLR1 946 may connect to the gate structure 906(412) of the readingtransistor 404 through another VG (not shown), and the WLR2 948 mayconnect to the gate structure 908(414) of the reading transistor 406through yet another VG (not shown).

In some embodiments, the MDs 920-928, VDs 930-934, and the non-shown VGsmay be disposed in a middle-end-of-line (MEOL) network. Theinterconnecting structure 940 and BL 942 may be disposed in a firstmetallization layer of a back-end-of-line (BEOL) network. The WLP 944,WLR1 946, and WLR2 948 may be disposed in a second metallization layerof the BEOL network. The second metallization layer can be disposed overthe first metallization layer, and the first metallization layer can bedisposed over the MEOL network.

Referring to FIG. 10 , a layout 1000 is depicted, in accordance withsome embodiments. The layout 1000 is similar to the layout 900 exceptthat the layout 1000 further includes features to form one or more dummygate structures. Thus, some of the reference numerals of FIG. 9 will bereused in the following discussions of FIG. 10 .

As shown, the layout 1000 further includes features 1002 and 1004 bothextending along the Y direction. The features 1002 and 1004 areconfigured to form dummy gate structures, which are hereinafter referredto as dummy gate structures, 1002 and 1004. In some embodiments, thedummy gate structures 1002-1004 may be similar as the gate structures410-414 of FIG. 4 (e.g., extending along the Y direction) but may nottravel across any active region. Accordingly, the dummy gate structures1002-1004 will not be adopted as an active gate structure toelectrically control current in a finished semiconductor device (e.g.,the memory device 400 of FIG. 4 ). As shown in FIG. 10 , the dummy gatestructure 1002 is disposed along one of the sides of the cell boundary901. The dummy gate structure 1004 is disposed between the activeregions 902A(408A) and 902B(408B).

FIG. 11 illustrates a flowchart of a method 1100 to define a firstactive region and a second active region over a substrate, according toone or more embodiments of the present disclosure. The first and secondactive regions may be laterally separated from each other by at leastone isolation structure. In some embodiments, the first active regionmay include a structure protruding from the substrate (e.g., a fin-basedstructure), and the second active region may include a number ofnanostructures (e.g., nanosheets, nanowires or otherwise semiconductorlayers with the dimensions of the order of a nanometer) alternatinglystacked on top of one another. Upon the first and second active regionsbeing defined, the method 1100 may be followed by the method 1800 ofFIG. 18 to form one or more non-GAA transistors and one or more GAAtransistors in the first active region and second active region,respectively, which will be discussed in further detail below.

The operations of the method 1100 may be associated with cross-sectionalviews of a memory device 1200 at respective fabrication stages as shownin FIGS. 12, 13, 14, 15, and 16 . For example, the memory device 1200may be similar to the memory device 300 of FIG. 3 , or the memory device400 of FIG. 4 . The cross-sectional view of FIGS. 12-16 may be cut alongline A-A′ as shown in FIGS. 3 and 4 . In some embodiments, the memorydevice 1200 may be included in or otherwise coupled to a microprocessor,another memory device, and/or other integrated circuit (IC). Also, FIGS.12-16 are simplified for a better understanding of the concepts of thepresent disclosure. Although the figures illustrate the memory device1200, it is understood the IC may include a number of other devices suchas inductors, resistor, capacitors, transistors, etc., which are notshown in FIGS. 12-16 , for purposes of clarity of illustration.

In brief overview, the method 1100 starts with operation 1102 in which asemiconductor substrate is provided. Next, the method 1100 proceeds tooperation 1104 in which a first region of the semiconductor substrate ismasked. Next, the method 1100 continues to operation 1106 in which asecond region of the semiconductor substrate is etched to form a recess.Next, in operation 1108, a number of first semiconductor layers and anumber of second semiconductor layers are epitaxially grown in thesecond region (the recess) to alternatingly stack on top of one another.Upon growing the first and second semiconductor layers in the secondregion, the method 1100 proceeds to operation 1110 in which a firstactive region and a second active region are defined.

Corresponding to operation 1102 of FIG. 11 , FIG. 12 is across-sectional view of the memory device 1200 that includes asemiconductor substrate 1202, at one of the various stages offabrication.

The semiconductor substrate 1202 includes a semiconductor materialsubstrate, for example, silicon. Alternatively, the semiconductorsubstrate 1202 may include other elementary semiconductor material suchas, for example, germanium. The semiconductor substrate 1202 may alsoinclude a compound semiconductor such as silicon carbide, galliumarsenic, indium arsenide, and indium phosphide. The semiconductorsubstrate 1202 may include an alloy semiconductor such as silicongermanium, silicon germanium carbide, gallium arsenic phosphide, andgallium indium phosphide. In one embodiment, the semiconductor substrate1202 includes an epitaxial layer. For example, the semiconductorsubstrate 1202 may have an epitaxial layer overlying a bulksemiconductor. Furthermore, the semiconductor substrate 1202 may includea semiconductor-on-insulator (SOI) structure. For example, thesemiconductor substrate 1202 may include a buried oxide (BOX) layerformed by a process such as separation by implanted oxygen (SIMOX) orother suitable technique, such as wafer bonding and grinding.

Corresponding to operation 1104 of FIG. 11 , FIG. 13 is across-sectional view of the memory device 1200 that includes a patternedmask 1304 formed on a top surface 1203 of the semiconductor substrate1202, at one of the various stages of fabrication.

The patterned mask 1304 covers a first region 1202A of the semiconductorsubstrate 1202 and includes an opening that exposes a second region1202B of the semiconductor substrate 1202. In an embodiment, the firstregion 1202A may include an active region defined for forming one ormore non-GAA transistors (e.g., 302 of FIG. 3 , 402 of FIG. 4 ), whichare configured as n-type transistors, and the second region 1202B mayinclude an active region defined for forming one or more GAA transistors(e.g., 304 of FIG. 3 , 404-406 of FIG. 4 ), which are also configured asn-type transistors. As such, the regions 1202A-B may be doped withp-type dopants. It is understood that the memory device 1200 mayalternatively have p-type transistors form in the regions 1202A-B.

The patterned mask 1304 may be a soft mask such as a patterned resistlayer, or a hard mask such as a dielectric material layer, or acombination thereof. In the illustrated embodiment of FIG. 13 , thepatterned mask 1304 includes a hard mask 1306 disposed on the region1202A and a patterned resist layer 1308 formed on the hard mask 1306 bya lithography process. The hard mask 1306 is etched to transfer theopening from the patterned resist layer 1308 to the hard mask 1306. Forexample, the hard mask 1306 includes silicon oxide, silicon nitride,silicon oxynitride, silicon carbide, silicon carbide nitride, siliconcarbide oxynitride, other semiconductor material, and/or otherdielectric material. In an embodiment, the hard mask 1306 has athickness ranging from about 1 nanometer (nm) to about 40 nm. The hardmask 1306 may be formed by thermal oxidation, chemical vapor deposition(CVD), atomic layer deposition (ALD), or any other appropriate method.An example photolithography process may include forming a resist layer,exposing the resist by a lithography exposure process, performing apost-exposure bake process, and developing the photoresist layer to formthe patterned photoresist layer. The lithography process may bealternatively replaced by other technique, such as e-beam writing,ion-beam writing, maskless patterning or molecular printing. In someembodiments, the patterned resist layer 1308 may be directly used as anetch mask for the subsequent etch process. The patterned resist layer1308 may be removed by a suitable process, such as wet stripping orplasma ashing, after the patterning of the hard mask 1306.

Corresponding to operation 1106 of FIG. 11 , FIG. 14 is across-sectional view of the memory device 1200 in which thesemiconductor substrate 1202 is etched to form a recess 1402, at one ofthe various stages of fabrication.

The semiconductor substrate 1202 in the second region 1202B is etched toform the recess 1402. The etching process is designed to selectivelyremove the semiconductor substrate 1202 in the second region 1202B usingthe hard mask 1306 as an etch mask. The etching process may be continuedto ensure that a bottom surface 1205 of the semiconductor substrate 1202is exposed in the recess 1402. A sidewall 1207 of the semiconductorsubstrate 1202 in the first region 1202A is also exposed defining anedge of the recess 1402. The etching process may include dry etch, wetetch, or a combination thereof. The patterned mask 1306 protects thesemiconductor substrate 1202 within the first region 1202A from etching.In various examples, the etching process may include a dry etch with asuitable etchant, such as fluorine-containing etching gas orchlorine-containing etching gas, such as C1₂, CC1₂F₂, CF₄, SF₆, NF₃,CH₂F₂ or other suitable etching gas. In some other examples, the etchingprocess may include a wet etch with a suitable etchant, such as ahydrofluoric acid (HF) based solution, a sulfuric acid (H₂SO₄) basedsolution, a hydrochloric (HCl) acid based solution, an ammoniumhydroxide (NH₄OH) based solution, other suitable etching solution, orcombinations thereof. The etching process may include more than onestep.

Corresponding to operation 1108 of FIG. 11 , FIG. 15 is across-sectional view of the memory device 1200 that includes a number offirst semiconductor layers 1502 (e.g., 1502 a, 1502 b, and 1502 c) and anumber of second semiconductor layers 1504 (e.g., 1504 a, 1504 b, and1504 c), at one of the various stages of fabrication.

In some embodiments, the first semiconductor layers 1502 a-c and thesecond semiconductor layers 1504 a-c are alternatingly disposed on topof one another (e.g., along the Z direction) in the recess 1402 (FIG. 14) to form a stack. For example, one of the second semiconductor layers,1504 a, is disposed over one of the first semiconductor layers, 1502 a,then another one of the first semiconductor layers, 1502 b, is disposedover the second semiconductor layer 1504 a, so on and so forth.

In various embodiments, the stack may include any number of alternatelydisposed semiconductor layers 1502 and 1504. The semiconductor layers1502 and 1504 may have different thicknesses. The semiconductor layers1502 may have different thicknesses from one layer to another layer. Thesemiconductor layers 1504 may have different thicknesses from one layerto another layer. The thickness of each of the semiconductor layers 1502and 1504 may range from few nanometers to few tens of nanometers. Thefirst layer of the stack may be thicker than other semiconductor layers1502 and 1504. For example, the layer 1502 a may be thicker than otherlayers 1502 b-c and 1504 a-c. In an embodiment, each of the firstsemiconductor layers 1502 a-c has a thickness ranging from about 5 nm toabout 20 nm, and each of the second semiconductor layers 1504 a-c has athickness ranging from about 5 nm to about 20 nm.

The two semiconductor layers 1502 and 1504 have different compositions.In various embodiments, the two semiconductor layers 1502 and 1504 havecompositions that provide for different oxidation rates and/or differentetch selectivity between the layers. In an embodiment, the semiconductorlayers 1502 include silicon germanium (Si_(1-x)Ge_(x)), and thesemiconductor layers 1504 include silicon (Si). In an embodiment, eachof the semiconductor layers 1504 is silicon that may be undoped orsubstantially dopant-free (i.e., having an extrinsic dopantconcentration from about 0 cm⁻³ to about 1×10¹⁷ cm⁻³), where forexample, no intentional doping is performed when forming the layers 1504(e.g., of silicon). Alternatively, the semiconductor layers 1504 may beintentionally doped. For example, each of the semiconductor layers 1504may be silicon that is doped with a p-type dopant such as boron (B),aluminum (Al), indium (In), and gallium (Ga) for forming a p-typechannel, or an n-type dopant such as phosphorus (P), arsenic (As),antimony (Sb), for forming an n-type channel. In some embodiments, eachof the semiconductor layers 1502 is Si_(1-x)Ge_(x) that includes lessthan 50% (x < 0.5) Ge in molar ratio. For example, Ge may comprise about15% to 35% of the semiconductor layers 1502 of Si_(1-x)Ge_(x) in molarratio. Furthermore, the semiconductor layers 1502 may include differentcompositions among them, and the semiconductor layers 1504 may includedifferent compositions among them.

In various embodiments, either of the semiconductor layers 1502 and 1504may include other materials, for example, a compound semiconductor suchas silicon carbide, gallium arsenide, gallium phosphide, indiumphosphide, indium arsenide, and/or indium antimonide, an alloysemiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/orGaInAsP, or combinations thereof. The materials of the semiconductorlayers 1502 and 1504 may be chosen based on providing differingoxidation rates and/or etch selectivity. The semiconductor layers 1502and 1504 may be doped or undoped, as discussed above.

In various embodiments, the semiconductor layers 1502 and 1504 areepitaxially grown from the bottom surface 1205 in the second region1202B. For example, each of the semiconductor layers 1502 and 1504 maybe grown by a molecular beam epitaxy (MBE) process, a chemical vapordeposition (CVD) process such as a metal organic CVD (MOCVD) process,and/or other suitable epitaxial growth processes. During the epitaxialgrowth, the crystal structure of the semiconductor substrate 1202extends upwardly (e.g., along the Z direction), resulting in thesemiconductor layers 1502 and 1504 having the same crystal orientationwith the semiconductor substrate 1202.

In the first region 1202A, the hard mask 1306 (FIG. 14 ) can function asa capping layer on the top surface 1203 of the semiconductor substrate1202, blocking epitaxial growth from taking place in the first region1202A. Although not shown, an optional dielectric layer may be formed toextend along the sidewall 1207. As such, the dielectric layer can coversthe sidewall 1207 thereby blocking epitaxial growth from originatingfrom the sidewall 1207 so that the epitaxially growth does not takeplace in lateral direction from the sidewall 1207 into the second region1202B. Therefore, in some embodiments, the epitaxial growth of thesemiconductor layers 1502 and 1504 are limited in the second region1202B. In some embodiments, after forming a desired number of thesemiconductor layers 1502 and 1504 (e.g., the third semiconductor layer1504 c), a polishing process (e.g., a chemical mechanical polishing(CMP) process) may be performed to level the first and second regions1202A and 1202B.

Corresponding to operation 1110 of FIG. 11 , FIG. 16 is across-sectional view of the memory device 1200 that includes a firstactive structure 1602A and a second active structure 1602B, at one ofthe various stages of fabrication.

The first active structure 1602A may be formed in the region 1202A whereno alternatingly stacked semiconductor layers (e.g., 1502 and 1504) areformed, and the second active structure 1602B may be formed in theregion 1202B where the alternatingly stacked semiconductor layers (e.g.,1502 and 1504) are formed. As will be discussed below, a correspondingregion of the first active structure 1602A is such defined as a regionor footprint where one or more non-GAA transistors (e.g., 302 of FIG. 3, 402 of FIG. 4 ) are to be formed (hereinafter “first active region1603A”), and a corresponding region of the second active structure 1602Bis such defined as a region or footprint where one or more GAAtransistors (.g., 304 of FIG. 3 , 404-406 of FIG. 4 ) are to be formed(hereinafter “second active region 1603B”)..

As shown in FIG. 16 , the first active structure 1602A is formed as afin-based structure protruding from the semiconductor substrate 1202,and the second active structure 1602B is formed as analternating-semiconductor layer column disposed over the semiconductorsubstrate 1202. In some embodiments, the first active structure 1602Amay be an integrally contiguous structure extended from thesemiconductor substrate 1202. The first active structure 1602A may beelongated along a lateral direction (e.g., the X direction). The secondactive structure 1602B includes a stack of semiconductor layers 1610 and1620 interleaved with each other.

In the formation of the first active structure 1602A and the secondactive structure 1602B, patterned masks 1625A and 1625B (shown in dottedlines) can be formed over the semiconductor substrate 1202 in theregions 1202A and 1202B, respectively. The patterned masks 1625A and1625B can define the footprint of the first active structure 1602A andthe second active structure 1602B (e.g., by masking the to-be formedactive structures 1602A-B), and one or more etching processes can beapplied to the semiconductor substrate 1202 in the first region 1202Aand the semiconductor layers 1502 and 1504 in the second region 1202B,respectively, to form the first active structure 1602A and the secondactive structure 1602B. Accordingly, the first and second active regions1603A and 1603B can be defined. In some embodiments, the semiconductorlayers 1610 a, 1620 a, 1610 b, 1620 b, 1610 c, and 1620 c may be theremaining portions of the semiconductor layers 1502 a, 1504 a, 1502 b,1504 b, 1502 c, and 1504 c, respectively. Upon the formation of thefirst active structure 1602A and the second active structure 1602B, thepatterned masks 1625A-B may be removed.

The one or more etching processes may include one or more dry etchingprocesses, wet etching processes, and other suitable etching techniques.For example, a dry etching process may implement an oxygen-containinggas, a fluorine-containing gas (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/orC₂F₆), a chlorine-containing gas (e.g., Cl₂, CHCl₃, CCl₄, and/or BCl₃),a bromine-containing gas (e.g., HBr and/or CHBR₃), an iodine-containinggas, other suitable gases and/or plasmas, and/or combinations thereof.For example, a wet etching process may comprise etching in dilutedhydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, asolution containing hydrofluoric acid (HF), nitric acid (HNO₃), and/oracetic acid (CH₃COOH), or other suitable wet etchant.

In some embodiments, the patterned masks 1625A-B used to form the activestructures 1602A-B may be formed in accordance with the respectiveactive features of a layout. In various embodiments, any of the layouts500-1000 of FIGS. 5-10 can be used to form the active structures1602A-B, and corresponding active regions 1603A-B. For example, upongrowing the semiconductor layers 1502 and 1504 in the correspondingregion over a semiconductor substrate (FIG. 15 ), the active features502A and 502B, as shown in FIGS. 5-8 , can be used to form the first andsecond active structures, 1602A and 1602B, respectively, and accordinglyto define the first and second active regions, 1603A and 1603B,respectively. In another example, upon growing the semiconductor layers1502 and 1504 in the corresponding region over a semiconductor substrate(FIG. 15 ), the active features 902A and 902B, as shown in FIGS. 9-10 ,can be used to form the first and second active structures, 1602A and1602B, respectively, and accordingly to define the first and secondactive regions, 1603A and 1603B, respectively.

After forming the active structures 1602A-B, one or more isolationstructures 1630 may be formed between the active structures 1602A-B. Theisolation structure 1630, which are formed of an insulation material,can electrically isolate neighboring active structures from each other.The insulation material may be an oxide, such as silicon oxide, anitride, the like, or combinations thereof, and may be formed by a highdensity plasma chemical vapor deposition (HDP-CVD), a flowable CVD(FCVD) (e.g., a CVD-based material deposition in a remote plasma systemand post curing to make it convert to another material, such as anoxide), the like, or combinations thereof. Other insulation materialsand/or other formation processes may be used. In an example, theinsulation material is silicon oxide formed by a FCVD process. An annealprocess may be performed once the insulation material is formed. Aplanarization process, such as a chemical mechanical polish (CMP)process, may remove any excess insulation material and form a topsurface of the insulation material and a top surface of the patternedmasks 1625A-B that are coplanar (not shown). The patterned masks 1625A-Bmay also be removed by the planarization process.

Next, the insulation material is recessed to form the isolationstructures 1630, as shown in FIG. 16 , which are sometimes referred toas shallow trench isolations (STIs). The isolation structures 1630 arerecessed such that the active structures 1602A-B protrude from betweenneighboring isolation structures 1630. Respective top surfaces of theisolation structures (STIs) 1630 may have a flat surface (asillustrated), a convex surface, a concave surface (such as dishing), orcombinations thereof. The top surfaces of the isolation structures 1630may be formed flat, convex, and/or concave by an appropriate etch. Theisolation structures 1630 may be recessed using an acceptable etchingprocess, such as one that is selective to the material of the isolationstructures 1630. For example, a dry etch or a wet etch using dilutehydrofluoric (DHF) acid may be performed to recess the isolationstructures 1630.

FIG. 17 illustrates a flowchart of another method 1700 to define thefirst active region 1603A and the second active region 1603B, accordingto one or more embodiments of the present disclosure. Similar as themethod 1100 of FIG. 11 , the method 1700 may be followed by the method1800 of FIG. 18 to form one or more non-GAA transistors and one or moreGAA transistors in the first active region and second active region,respectively, which will be discussed in further detail below. Theoperations of the method 1700 will be briefly discussed as follows, withreference to the cross-sectional views of FIGS. 12-16 .

For example, the method 1700 starts with operation 1702 in which thesemiconductor substrate 1202 is provided (FIG. 12 ). Next, differentfrom the method 1100 (e.g., instead of growing the semiconductor layers1502 and 1504 in the recess 1402), the method 1700 proceeds to operation1704 in which the first semiconductor layers 1502 and the secondsemiconductor layers 1504 are epitaxially grown over the semiconductorsubstrate 1202. The first and second semiconductor layer 1502 and 1504are alternatingly stacked on top of one another. Next, the method 1700proceeds to operation 1706 in which the second region 1202B is masked,followed by operation 1708 in which the first region 1202A is etched toform a recess. Next, in operation 1710, a third semiconductor layer,similar to the second semiconductor layer, is epitaxially grown in therecess of the first region. Upon growing the third semiconductor layerin the first region, similar as the method 1100, the method 1700proceeds to operation 1712 in which the first active structure 1602A andthe second active structure 1602B are defined.

As mentioned above, either of the methods 1100 (FIG. 11 ) and 1700 (FIG.17 ) can be followed by the method 1800 (FIG. 18 ). In variousembodiments, the operations of the method 1800 can form one or morenon-GAA transistors and one or more GAA transistors in the first activeregion 1603A and second active region 1603B, respectively.

Referring to FIG. 18 , a flowchart of the method 1800 to form at leastone non-GAA transistor and at least one GAA transistor in the firstactive region 1603A and second active region 1603B, respectively, isdepicted, according to one or more embodiments of the presentdisclosure. The operations of the method 1800 may be associated withcross-sectional views of the memory device 1200 at respectivefabrication stages as shown in FIGS. 19A, 19B, 19C, 20, 21, 22, 23, 24,25, 26, 27A, 27B, 27C, and 28 . The cross-sectional view of FIGS. 19A,20-27A, and 28 may be cut along line A-A′ as shown in FIGS. 3 and 4 ;FIGS. 19B and 27B may be cut along line B-B′ as shown in FIGS. 3 and 4 ;and FIGS. 19C and 27C may be cut along line C-C′ as shown in FIGS. 3 and4 . FIGS. 19A-28 are simplified for a better understanding of theconcepts of the present disclosure, and thus, it is understood thememory device 1200 may include a number of other devices such asinductors, resistor, capacitors, transistors, etc., which are not shownin FIGS. 19A-28 , for purposes of clarity of illustration.

In brief overview, the method 1800 starts with operation 1802 in whichdummy gate structures are formed. Next, the method 1800 proceeds tooperation 1804 in which end portions of the second active structure areremoved. Next, the method 1800 continues to operation 1806 in whichinner spacers are formed in the second active structure. Next, themethod 1800 continues to operation 1808 in which source/drain structurescoupled to the second active structure are formed. Next, the method 1800continues to operation 1810 in which end portions of the first activestructure are removed. Next, the method 1800 continues to operation 1812source/drain structures coupled to the first active structure areformed. Next, the method 1800 continues to operation 1814 in which anILD is formed. Next, the method 1800 continues to operation 1816 inwhich the dummy gate structures are first removed and the firstsemiconductor layers are then removed from the second active structure.Next, the method 1800 continues to operation 1818 in which active gatestructures are formed. Next, the method 1800 continues to operation 1820in which interconnecting structures are formed.

Corresponding to operation 1802 of FIG. 18 , FIG. 19A is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), that includes a first dummy gatestructure 1902 and a second dummy gate structure 1912, at one of thevarious stages of fabrication. For clarity of illustration, FIG. 19Billustrates a corresponding cross-sectional view of the memory device1200, cut along line B-B′ (e.g., as indicated in FIGS. 3-4 ); and FIG.19C illustrates a corresponding cross-sectional view of the memorydevice 1200, cut along line C-C′ (e.g., as indicated in FIGS. 3-4 ).

Each of the dummy gate structures includes a dummy gate dielectric, adummy gate, and a hard mask. For example in FIGS. 19A and 19B, the firstdummy gate structure 1902 includes a dummy gate dielectric 1904 formedover the first active structure 1602A, a dummy gate 1906 formed over thedummy gate dielectric 1904, and a hard mask 1908 formed over the dummygate 1906; and for example in FIGS. 19A and 19C, the second dummy gatestructure 1912 includes a dummy gate dielectric 1914 formed over thesecond active structure 1602B, a dummy gate 1916 formed over the dummygate dielectric 1914, and a hard mask 1918 formed over the dummy gate1916.

As shown in in FIGS. 19A-C, the dummy gate structure 1902 is formed overa top surface and around sidewalls of the first active structure 1602A;and the dummy gate structure 1912 is formed over a top surface andaround sidewalls of the second active structure 1602B. To form the dummygate structure 1902 (which is used as a representative example), adielectric layer is formed over the first active structure 1602A. Thedielectric layer may be, for example, silicon oxide, silicon nitride,multilayers thereof, or the like, and may be deposited or thermallygrown. A gate layer is formed over the dielectric layer, and a masklayer is formed over the gate layer. The gate layer may be depositedover the dielectric layer and then planarized, such as by a CMP. Themask layer may be deposited over the gate layer. The gate layer may beformed of, for example, polysilicon, although other materials may alsobe used. The mask layer may be formed of, for example, silicon nitrideor the like. After the layers (e.g., the dielectric layer, the gatelayer, and the mask layer) are formed, the mask layer may be patternedusing acceptable photolithography and etching techniques to form thehard mask 1908. The pattern of the hard mask 1908 then may betransferred to the gate layer and the dielectric layer by an acceptableetching technique to form the dummy gate 1906 and the underlying dummygate dielectric 1904, respectively. The dummy gate structure 1912 can beconcurrently or respectively formed using the similar operations, asdiscussed above.

After forming the dummy gate structures 1902 and 1912, gate spacers 1910and 1920 may be formed to extend along respective sidewalls of the dummygate structures 1902 and 1912, as illustrated in FIG. 19A. The gatespacers 1910-1920 can be formed using a spacer pull down formationprocess. The gate spacers 1910-1920 can also be formed by a conformaldeposition of a dielectric material (e.g., silicon oxide, siliconnitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitablecombination of those materials) followed by a directional etch (e.g.,RIE).

In some embodiments, the dummy gate structures 1902 and 1912 may beformed according to the gate features of each of the layouts 500-1000(FIGS. 5-10 ). Using the layout 500 of FIG. 5 as an example, thepatterns of the hard masks 1908 and 1918 may be formed according to thegate features 504 and 506, respectively. As such, the dummy gatestructure 1902 can straddle or otherwise cover a central portion (e.g.,the channel of a subsequently formed non-GAA transistor of the memorydevice 1200) of the first active structure 1602A, which is formed basedon the active feature 502A; and the dummy gate structure 1912 canstraddle or otherwise cover a central portion (e.g., the channel of asubsequently formed GAA transistor of the memory device 1200) of thesecond active structure 1602B, which is formed based on the activefeature 502B. Further, each of the dummy gate structures 1902 and 1912may have a lengthwise direction (e.g., along the Y direction)substantially perpendicular to the lengthwise direction (e.g., along theX direction) of the active structures 1602A-B. In various embodiments,the dummy gate structures 1902 and 1912 may be subsequently replaced byrespective active gate structures, with the gate spacers 1910 and 1920substantially intact. Consequently, when the memory device 1200 isfinished, such active gate structures may function as the gates of anon-GAA transistor and a GAA transistor, respectively, of the memorydevice 1200 (similar as the memory device 300 of FIG. 3 ), which will befurther shown in FIGS. 27A-C.

Although two dummy gate structures are shown in FIGS. 19A-C, it isunderstood that the memory device 1200 can have more than two dummy gatestructures while remaining within the scope of the present disclosure.For example, when using the layouts 600-700 of FIGS. 6-7 to form dummygate structures, in addition to the dummy gate structures over theactive structures (formed based on the gate features 504 and 506), atleast one dummy gate structure can be formed between the activestructures based on the gate feature 604. Such an additional dummy gatestructure, also with a gate spacer extending along its sidewalls, can beformed over the isolation structure 1630 between the active structures1602A-B and may not be replaced by an active gate structure.Consequently, when the memory device 1200 is finished, this “remaining”dummy gate structure may be disposed between a non-GAA transistor and aGAA transistor of the memory device 1200 (similar as the memory device300 of FIG. 3 except for including at least one additional dummy gatestructure), which will be further shown in FIG. 29 .

In another example, when using the layout 900 of FIG. 9 to form dummygate structures, at least three dummy gate structures can be formed. Thepatterns of the hard masks 1908 and 1918 shown in FIGS. 19A-C may beformed according to the gate features 904 and 906, respectively. Assuch, the dummy gate structure 1902 can straddle or otherwise cover acentral portion (e.g., the channel of a subsequently formed non-GAAtransistor of the memory device 1200) of the first active structure1602A, which is formed based on the active feature 902A; and the dummygate structure 1912 can straddle or otherwise cover a first portion(e.g., the channel of one of two subsequently formed GAA transistors ofthe memory device 1200) of the second active structure 1602B, which isformed based on the active feature 902B. Additionally, the pattern of athird hard mask (not shown) may be formed according to the gate feature908, and thus, another dummy gate structure (not shown) can straddle orotherwise cover a second portion (e.g., the channel of the other of twosubsequently formed GAA transistors of the memory device 1200) of thesecond active structure 1602B. In various embodiments, these three dummygate structures may be subsequently replaced by respective active gatestructures, with the corresponding gate spacers substantially intact.Consequently, when the memory device 1200 is finished, such active gatestructures may function as the gates of a non-GAA transistor, a firstGAA transistor, and a second GAA transistor, respectively, of the memorydevice 1200 (similar as the memory device 400 of FIG. 4 ), which will befurther shown in FIG. 30 .

In yet another example, when using the layout 1000 of FIG. 10 to formdummy gate structures, in addition to the three dummy gate structuresover the active structures (formed based on the gate features 904, 906,and 908), at least one dummy gate structure can be formed between theactive structures based on the gate feature 1004. Such an additionaldummy gate structure, also with a gate spacer extending along itssidewalls, can be formed over the isolation structure 1630 between theactive structures 1602A-B and may not be replaced by an active gatestructure. Consequently, when the memory device 1200 is finished, this“remaining” dummy gate structure may be disposed between a non-GAAtransistor and two GAA transistors of the memory device 1200 (similar asthe memory device 400 of FIG. 4 except for including at least oneadditional dummy gate structure), which will be further shown in FIG. 31.

Although the dummy gate structure 1902 shown in FIGS. 19A-C straddlesthe active structure 1602A with its sidewalls along the X directionexposed, it is understood that the memory device 1200 can include thedummy gate structure further extending one of the sidewalls along the Xdirection, while remaining within the scope of the present disclosure.For example, when using the layout 800 of FIG. 8 to form dummy gatestructures, as the gate feature 504 only travels across an end portionof the active feature 802A (used to form the first active structure1602A), the dummy gate structure 1902, in addition to straddling the topsurface and sidewalls (along the Y direction) of the first activestructure 1602A, may extend along one of the sidewalls (along the Xdirection) that faces opposite to the second active structure 1602B. Invarious embodiments, the dummy gate structures 1902 and 1912 may besubsequently replaced by respective active gate structures, with thegate spacers 1910 and 1920 substantially intact. Consequently, when thememory device 1200 is finished, such active gate structures may functionas the gates of a non-GAA transistor and a GAA transistor, respectively,of the memory device 1200. Specifically, the non-GAA transistor may haveonly one source/drain structure formed opposite to the sidewall alongwhich the corresponding active gate structure extends (similar as thememory device 300 of FIG. 3 except for not including the source/drainstructure 316), which will be further shown in FIG. 32 . In someembodiments, such a transistor with only one source/drain structure issometimes referred to as a MOS capacitor.

In the following discussions of the method 1800 for making the memorydevice 1200, the layout 500 of FIG. 5 will be focused. In other words,the cross-sectional views of the memory device 1200 in FIGS. 20-28 willnot illustrate an additional dummy gate structure between activestructures 1602A-B, a third active/dummy gate structure formed over thesecond active structure 1602B, or a MOS capacitor. The cross-sectionalview of such other embodiments of the memory device 1200, which can beformed based on the layouts shown in FIGS. 6-10 , will be shown in FIGS.29-32 , respectively.

Corresponding to operation 1804 of FIG. 18 , FIG. 20 is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), in which end portions of the secondactive structure 1602B (along the X direction) are removed, at one ofthe various stages of fabrication.

In some embodiments, when removing the end portions of the second activestructure 1602B, the first active structure 1602A (or the first activeregion 1603A) may be covered by a blocking mask 2001. The blocking mask2001 is formed to overlay the first active structure 1602A whileremaining the second active structure 1602B exposed. The blocking mask2001 may be formed to have a sufficiently great thickness (or height)such that the top surface and sidewalls of the first active structure1602A are fully covered, as shown in FIG. 20 . Formation of the blockingmask 2001 may allow one or more processes, which will be discussedbelow, to be performed on the second active structure 1602B only. Theblocking mask 2001 may be formed of a material relatively resistant toetchants that can etch SiGe such as, for example, silicon oxide, siliconnitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitablecombinations of those materials.

Upon covering the first active structure 1602A (or the first activeregion 1603A) with the blocking mask 2001, the dummy gate structure 1912together with the gate spacer 1920 can be used as a mask to etch the endportions of the second active structure 1602B, which results in thesecond active structure 1602B in the second active region 1603B havingan alternatingly stack of the remaining portions of the semiconductorlayers 1610 and 1620. For example, semiconductor layers 2010 a, 2020 a,2010 b, 2020 b, 2010 c, and 2020 c of the second active structure 1602B,as shown in FIG. 20 , are the remaining portions of the semiconductorlayers 1610 a, 1620 a, 1610 b, 1620 b, 1610 c, and 1620 c, respectively.In some embodiments, the semiconductor layers 2010 a-c and 2020 a-c maysometimes be referred to as nanostructures 2010 a-c and 2020 a-c.

Corresponding to operation 1806 of FIG. 18 , FIG. 21 is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), that includes inner spacers 2102formed along respective etched ends of each of the semiconductor layers2010 a-c (along the X direction), at one of the various stages offabrication.

To form the inner spacers 2102, respective end portions of each of thesemiconductor layers 2010 a-c may first be removed. During the removalof the respective end portions of the semiconductor layers 2010 a-c, thefirst active structure 1602A may remain covered by the blocking mask2001, which allows the first active structure 1602A to remain intact.The end portions of the semiconductor layers 2010 a-c can be removed(e.g., etched) using a “pull-back” process to pull the semiconductorlayers 2010 a-c back by an initial pull-back distance such that the endsof the semiconductor layers 2010 a-c terminate underneath (e.g., alignedwith) the gate spacer 1920. Although in the illustrated embodiment ofFIG. 21 , the etched ends of each of the semiconductor layers 2010 a-care approximately aligned with the sidewalls of the gate spacer 1920, itis understood that the pull-back distance (i.e., the extent to whicheach of the semiconductor layers 2010 a-c is etched, or pulled-back) canbe arbitrarily increased or decreased. In an example where thesemiconductor layers 2020 a-c include Si, and the semiconductor layers2010 a-c include Si_(1-x)Ge_(x), the pull-back process may include ahydrogen chloride (HCL) gas isotropic etch process, which etches SiGewithout attacking Si. As such, the semiconductor layers 2020 a-c mayremain intact during this process.

Next, the inner spacers 2102 can be formed along the etched ends of eachof the semiconductor layers 2010 a-c, with the first active structure1602A covered by the blocking mask 2001. In some embodiments, the innerspacers 2102 can be formed conformally by chemical vapor deposition(CVD), or by monolayer doping (MLD) of nitride followed by spacer RIE.The inner spacers 2102 can be deposited using, e.g., a conformaldeposition process and subsequent isotropic or anisotropic etch back toremove excess spacer material on the sidewalls of the second activestructure 1602B and on a surface of the semiconductor substrate 1202. Amaterial of the inner spacers 2102 can be formed from the same ordifferent material as the gate spacer 1920 (e.g., silicon nitride). Forexample, the inner spacers 2102 can be formed of silicon nitride,silicoboron carbonitride, silicon carbonitride, silicon carbonoxynitride, or any other type of dielectric material (e.g., a dielectricmaterial having a dielectric constant k of less than about 5)appropriate to the role of forming an insulating gate sidewall spacersof transistors.

Corresponding to operation 1808 of FIG. 18 , FIG. 22 is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), that includes source/drainstructures 2202 and 2204 in the second active region 1603B, at one ofthe various stages of fabrication. The source/drain structures 2202 and2204 are coupled to respective ends of the second active structure1602B.

During the formation of the source/drain structures 2202 and 2204, thefirst active structure 1602A may remain covered by the blocking mask2001. The source/drain structures 2202 and 2204 may be formed using anepitaxial layer growth process on exposed ends of each of thesemiconductor layers 2020 a-c. In some embodiments, a bottom surface ofthe source/drain structures 2202 and 2204 may be leveled with the topsurface of the isolation structure 1630, as shown in solid lines of FIG.22 . Accordingly, the source/drain structures 2202 and 2204 may have aheight, H₁. In some other embodiments, the bottom surface of thesource/drain structures 2202 and 2204 may be lower than the top surfaceof the isolation structure 1630, as shown in dotted lines of FIG. 22 .Accordingly, the source/drain structures 2202 and 2204 may have aheight, H₂.

The source/drain structures 2202 and 2204 are electrically coupled tothe semiconductor layers 2020 a-c. In various embodiments, thesemiconductor layers 2020 a-c may collectively function as the channelof a GAA transistor, hereinafter GAA transistor 2210. It is noted thatat this stage of fabrication, the GAA transistor 2210 is not finishedyet, in some embodiments. Referring again to FIG. 3 , the GAA transistor2210, upon being finished, may be similar to the GAA transistor 304.Accordingly, the semiconductor layers 2020 a-c may correspond to thesemiconductor layers 342 a-c, respectively; and the source/drainstructures 2202 and 2204 may correspond to the source/drain structures320 and 322, respectively.

In-situ doping (ISD) may be applied to form doped source/drainstructures 2202 and 2204, thereby creating the junctions for the GAAtransistor 2210. N-type and p-type FETs are formed by implantingdifferent types of dopants to selected regions (e.g., the source/drainstructures 2202 and 2204) of the device to form the junction(s). N-typedevices can be formed by implanting arsenic (As) or phosphorous (P), andp-type devices can be formed by implanting boron (B).

Corresponding to operation 1810 of FIG. 18 , FIG. 23 is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), in which end portions of the firstactive structure 1602A (along the X direction) are removed, at one ofthe various stages of fabrication.

In some embodiments, when removing the end portions of the first activestructure 1602A, the partially formed GAA transistor 2210 may be coveredby a blocking mask 2301. The blocking mask 2301 is formed to overlay thepartially formed GAA transistor 2210 while remaining the first activestructure 1602A exposed. The blocking mask 2301 may be formed to have asufficiently great thickness (or height) such that the partially formedGAA transistor 2210 is fully covered, as shown in FIG. 23 . Formation ofthe blocking mask 2301 may allow one or more processes, which will bediscussed below, to be performed on the first active structure 1602Aonly. The blocking mask 2301 may be formed of a material relativelyresistant to etchants that can etch SiGe such as, for example, siliconoxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or anysuitable combinations of those materials.

Upon covering the partially formed transistor 2210 with the blockingmask 2301, the dummy gate structure 1902 together with the gate spacer1910 can be used as a mask to etch the end portions of the first activestructure 1602A, which results in the first active structure 1602Ahaving its sidewalls (or ends) along the X direction exposed to formrespective source/drain structures.

Corresponding to operation 1812 of FIG. 18 , FIG. 24 is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), that includes source/drainstructures 2402 and 2404 in the first active region 1603A, at one of thevarious stages of fabrication. The source/drain structures 2402 and 2404are coupled to respective ends of the first active structure 1602A.

During the formation of the source/drain structures 2402 and 2404, thepartially formed GAA transistor 2210 may remain covered by the blockingmask 2301. The source/drain structures 2402 and 2404 may be formed usingan epitaxial layer growth process on the exposed ends of the firstactive structure 1602A. In some embodiments, a bottom surface of thesource/drain structures 2402 and 2404 may be leveled with the topsurface of the isolation structure 1630, as shown in of FIG. 24 .Accordingly, the source/drain structures 2402 and 2404 may have aheight, H₃, which is about equal to H₁ but less than H₂ (FIG. 22 ).

The source/drain structures 2402 and 2404 are electrically coupled tothe first active structure 1602A. In various embodiments, the firstactive structure 1602A may function as the channel of a non-GAAtransistor, hereinafter non-GAA transistor 2410. It is noted that atthis stage of fabrication, the non-GAA transistor 2410 is not finishedyet, in some embodiments. Referring again to FIG. 3 , the non-GAAtransistor 2410, upon being finished, may be similar to the non-GAAtransistor 302. Accordingly, the first active structure 1602A maycorrespond to the protruding structure 332; and the source/drainstructures 2402 and 2404 may correspond to the source/drain structures316 and 318, respectively.

In-situ doping (ISD) may be applied to form doped source/drainstructures 2402 and 2404, thereby creating the junctions for the non-GAAtransistor 2410. N-type and p-type FETs are formed by implantingdifferent types of dopants to selected regions (e.g., the source/drainstructures 2402 and 2404) of the device to form the junction(s). N-typedevices can be formed by implanting arsenic (As) or phosphorous (P), andp-type devices can be formed by implanting boron (B).

Corresponding to operation 1814 of FIG. 18 , FIG. 25 is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), that includes an interlayerdielectric (ILD) 2500, at one of the various stages of fabrication. TheILD 2500 may sometimes be referred to as ILD0. The ILD 2500 can beformed by depositing a dielectric material in bulk over the partiallyformed GAA transistor 2210 and non-GAA transistor 2410, and polishingthe bulk oxide back (e.g., using CMP) to the level of the dummy gates1906 and 1916, which causes the hard masks 1908 and 1918 to be removed.As such, the dummy gates 1906 and 1916 can be exposed. The dielectricmaterial of ILD 2500 includes silicon oxide, phosphosilicate glass(PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass(BPSG), undoped silicate glass (USG), and combinations thereof.

Corresponding to operation 1816 of FIG. 18 , FIG. 26 is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), in which the dummy gate structures1902 and 1912 are first removed and the semiconductor layers 2010 a-care then removed, at one of the various stages of fabrication.

Subsequently to forming the ILD 2500 and exposing the dummy gates 1906and 1916 (FIG. 25 ), the dummy gate structures 1902 and 1912 areremoved. The dummy gate structures 1902 and 1912 can be removed by aknown etching process, e.g., RIE or chemical oxide removal (COR). Afterthe removal of the dummy gate structure 1902, the top surface of thefirst active structure 1602A is exposed. Although not shown in thecross-sectional view of FIG. 26 , it is appreciated that in addition tothe top surface, the sidewalls of the first active structure 1602A(facing the Y direction) may be exposed. Similarly, after the removal ofthe dummy gate structure 1912, a top surface of the semiconductor layer2020 c us exposed. Although not shown in the cross-sectional view ofFIG. 26 , it is appreciated that in addition to the top surface, thesidewalls of each of the semiconductor layers 2010 a-c and 2020 a-c(facing the Y direction) may be exposed. Next, the semiconductor layers2010 a-c are removed by applying a selective etch (e.g., a hydrochloricacid (HCl)). After the removal of the semiconductor layers 2010 a-c,respective bottom surface and top surface of each of the semiconductorlayers 2020 a-c may be exposed.

Corresponding to operation 1818 of FIG. 18 , FIG. 27A is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), that includes a first active gatestructure 2702 and a second active structure 2712, at one of the variousstages of fabrication. For clarity of illustration, FIG. 27B illustratesa corresponding cross-sectional view of the memory device 1200, cutalong line B-B′ (e.g., as indicated in FIGS. 3-4 ); and FIG. 27Cillustrates a corresponding cross-sectional view of the memory device1200, cut along line C-C′ (e.g., as indicated in FIGS. 3-4 ).

Each of the active gate structures includes a gate dielectric and a gatemetal, in some embodiments. For example in FIGS. 27A-C, the first activegate structure 2702 includes a gate dielectric 2704 and a gate metal2706; and the active gate structure 2712 includes a gate dielectric 2714and a gate metal 2716.

The gate dielectric 2704 is in direct contact with the first activestructure 1602A. The gate dielectric 2714 wraps around each of thesemiconductor layers 2020 a-c. As further illustrated in FIGS. 27B-C,respectively, the gate dielectric 2704 is formed to straddle the topsurface and sidewalls of the first active structure 1602A, and the gatedielectric 2714 is formed to wrap around each of the semiconductorlayers 2020 a-c (e.g., the top/bottom surface and sidewallsperpendicular to the Y direction). The gate dielectrics 2704 and 2714may be formed of different high-k dielectric materials or a similarhigh-k dielectric material. Example high-k dielectric materials includea metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, andcombinations thereof. The gate dielectrics 2704 and 2714 may include astack of multiple high-k dielectric materials. The gate dielectrics 2704and 2714 can be concurrently or respectively deposited using anysuitable method, including, for example, molecular beam deposition(MBD), atomic layer deposition (ALD), PECVD, and the like. In someembodiments, the gate dielectrics 2704 and 2714 may optionally include asubstantially thin oxide (e.g., SiO_(x)) layer.

The gate metal 2706 can straddle the top surface and sidewalls of thefirst active structure 1602A with the gate dielectric 2704 disposedtherebetween. The gate metal 2716 can wrap around each of thesemiconductor layers 2020 a-c with the gate dielectric 2714 disposedtherebetween. As further illustrated in FIGS. 27B-C, respectively, thegate metal 2706 is formed to straddle the top surface and sidewalls ofthe first active structure 1602A, with the gate dielectric disposedtherebetween; and the gate dielectric 2716 is formed to wrap around eachof the semiconductor layers 2020 a-c (e.g., the top/bottom surface andsidewalls perpendicular to the Y direction), with the gate dielectric2714 disposed therebetween. Specifically, the gate metal 2716 caninclude a number of gate metal sections abutted to each other along theZ direction. Each of the gate metal sections can extend not only along ahorizontal plane (e.g., the plane expanded by the X direction and the Ydirection), but also along a vertical direction (e.g., the Z direction).As such, two adjacent ones of the gate metal sections can adjointogether to wrap around a corresponding one of the semiconductor layers2020 a-c, with the gate dielectric 2714 disposed therebetween.

The gate metals 2706 and 2716 may be formed of different metal materialsor a similar metal material. The gate metals 2706 and 2716 may eachinclude a stack of multiple metal materials. For example, each of thegate metals 2706 and 2716 may be a P-type work function layer, an N-typework function layer, multi-layers thereof, or combinations thereof. Thework function layer may also be referred to as a work function metal.Example P-type work function metals that may be included in the gatestructures for P-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi₂,MoSi₂, TaSi₂, NiSi₂, WN, other suitable P-type work function materials,or combinations thereof. Example N-type work function metals that may beincluded in the gate structures for N-type devices include Ti, Ag, TaAl,TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type workfunction materials, or combinations thereof. A work function value isassociated with the material composition of the work function layer, andthus, the material of the work function layer is chosen to tune its workfunction value so that a target threshold voltage V_(t) is achieved inthe device that is to be formed. The work function layer(s) may bedeposited by CVD, physical vapor deposition (PVD), ALD, and/or othersuitable process.

In some embodiments, upon the formation of the active gate structures2702 and 2712, the GAA transistor 2210 and the non-GAA transistor 2410may be finished. For example, the GAA transistor 2210 may include thegate structure 2712, source/drain structure 2202, and source/drainstructure 2404 functioning as its gate, source, and drain, respectively;and the non-GAA transistor 2410 may include the gate structure 2702,source/drain structure 2402, and source/drain structure 2204 functioningas its gate, source, and drain, respectively.

To operate the GAA transistor 2210 and non-GAA transistor 2410, forexample, as an anti-fuse memory cell, various interconnecting structuresmay be formed. For example, the non-GAA transistor 2410 may function asa programming transistor of the anti-fuse memory cell (e.g., 110 of FIG.1 ), and the GAA transistor 2210 may function as a reading transistor ofthe anti-fuse memory cell (e.g., 120 of FIG. 1 ). Variousinterconnecting structures may be formed, for example, to allow anelectrical connection between the drain of the non-GAA programmingtransistor (source/drain structure 2404) and the source of the GAAreading transistor (source/drain structure 2202), to electricallyconnect the gate of the non-GAA programming transistor (active gatestructure 2702) to a WLP, to electrically connect the gate of the GAAreading transistor (active gate structure 2712) to a WLR, and toelectrically connect the drain of the GAA reading transistor(source/drain structure 2204) to a BL.

Corresponding to operation 1820 of FIG. 18 , FIG. 28 is across-sectional view of the memory device 1200, cut along line A-A′(e.g., as indicated in FIGS. 3-4 ), that includes a number ofinterconnecting structures (e.g., contacts) 2802, 2804, 2806, 2812,2814, and 2816, at one of the various stages of fabrication. In someembodiments, the interconnecting structures 2802, 2804, 2806 provideelectrical connection to the non-GAA programming transistor 2410; andthe interconnecting structures 2812, 2814, and 2816 provide electricalconnection to the GAA reading transistor 2210.

As shown, the interconnecting structure 2802 is coupled to the activegate structure 2702 (or to the gate metal 2706); the interconnectingstructure 2804 is coupled to the source/drain structure 2402; theinterconnecting structure 2806 is coupled to the source/drain structure2404; the interconnecting structure 2812 is coupled to the active gatestructure 2712 (or to the gate metal 2716); the interconnectingstructure 2814 is coupled to the source/drain structure 2202; and theinterconnecting structure 2816 is coupled to the source/drain structure2204.

In various embodiments, to operate the GAA transistor 2210 and non-GAAtransistor 2410 as the reading transistor and programming transistor ofan anti-fuse memory cell, respectively, an interconnecting structure(e.g., which can be formed by the feature 534 of FIG. 5 , but is notshown in FIG. 28 ) can be established between the source/drain structure2404 (which functions as the drain the of the non-GAA transistor 2410)and the source/drain structure 2202 (which functions as the source ofthe GAA transistor 2210) through the interconnecting structures 2806 and2814, respectively; a WLP can be electrically connected to the activegate structure 2702 (which functions as the gate of the non-GAAtransistor 2410); a WLR can be electrically connected to the active gatestructure 2712 (which functions as the gate of the GAA readingtransistor 2210); a BL can be electrically connected to the source/drainstructure 2204 (which functions as the drain of the GAA readingtransistor 2210).

Each of the interconnecting structures may extend through another ILD2800 to couple to the respective structure. The ILD 2800, formed of thesimilar dielectric material as the ILD 2500, may sometimes be referredto as ILD 1, with respect to ILD 0 (the ILD 2500). The interconnectingstructure 2802 may further extend through a dielectric hard mask 2803(e.g., silicon nitride) to couple to the active gate structure 2702; andthe interconnecting structure 2812 may further extend through adielectric hard mask 2813 (e.g., silicon nitride) to couple to theactive gate structure 2712. Such dielectric hard masks may be formedsubsequently to forming the active gate structures and prior to formingthe interconnecting structures. For example, upon forming the activegate structures 2702 and 2712, an etching process may be performed torecess the active gate structures 2702 and 2712. The recessed activegate structures are then filled with a dielectric material (e.g.,silicon nitride), followed by a planarization process (e.g., a CMP), soas to form the dielectric hard masks 2803 and 2813.

Each of the interconnecting structures 2802-2816 may include ametal-containing material such as copper, aluminum, tungsten, the like,combinations thereof, or multi-layers thereof. For example, afterforming the dielectric hard masks 2803 and 2813, the ILD 2800 isdeposited over the memory device 1200. Next, one or more contact holesare formed (e.g., by at least one patterning process) to extend throughthe ILD 2800 and selectively the dielectric hard mask 2803 or 2813 toexpose each of the structures (e.g., 2702, 2402, 2404, 2712, 2202,2204). Such contact holes are then filled with the metal-containingmaterial by, e.g., electroplating, electroless plating, or othersuitable methods to form the interconnecting structures 2802-2816. Afterthe formation of the interconnecting structures, a planarizationprocess, such as a CMP, may be performed to remove the excess portionsof the metal-containing material.

Although, in FIG. 28 , each of the interconnecting structures 2802-2816is illustrated as a single via structure, it should be understood thatsome of the interconnecting structures 2802-2816 may include multiplestructures that are formed of a similar metal-containing material andconnected to each other. For example, each of the interconnectingstructures 2804, 2806, 2814, and 2816 may include an MD (formed as aslot or trench structure) and a VD (formed as a via structure), asdiscussed above with respect to FIGS. 5-10 .

Although not shown, each of the interconnecting structures may furtherinclude a barrier layer. For example, a bottom surface and sidewalls ofeach of the interconnecting structures may be surrounds by such abarrier layer. The barrier layer can include an electrically conductivematerial such as titanium nitride, although other materials, such astantalum nitride, titanium, tantalum, or the like, may alternatively beutilized. The barrier layer may be formed using a CVD process, such asPECVD. However, other alternative processes, such as sputtering, metalorganic chemical vapor deposition (MOCVD), or ALD, may alternatively beused.

FIG. 29 illustrates a cross-sectional view of another embodiment of thememory device 1200, which can be made based on the layout 600 FIG. 6 orlayout 700 of FIG. 7 . Referring again to FIGS. 6-7 , the layouts 600and 700 each include one or more features (e.g., 602 and 604) configuredto form dummy gate structures that will not be replaced by active gatestructures.

As shown in FIG. 29 , the memory device 1200 further includes dummy gatestructures 2900 and 2920, when compared to the embodiment shown in FIG.28 that is made based on the layout 500 of FIG. 5 . The dummy gatestructures 2900 and 2920 can be formed using the features 602 and 604(FIGS. 6-7 ), respectively, at operation 1802 of FIG. 18 . For example,the dummy gate structures may be formed concurrently with the dummy gatestructures 1902 and 1912 that will be replaced by respective active gatestructures at operations 1816 and 1818. Thus, each of the dummy gatestructures 1902 and 1912 includes the similar configuration as the dummygate structures 2900 and 2920 except that the dummy gate structures 2900and 2920 are formed over the isolation structures 1630 (e.g., not tooverlay any active region).

For example, the dummy gate structure 2900, formed over the isolationstructure 1630 opposite the active region 1603B from the active region1603A, includes a dummy gate dielectric 2902 and a dummy gate 2904, witha spacer 2906 extending along 2900′s sidewalls; and the dummy gatestructure 2920, formed over the isolation structure 1630 between theactive regions 1603A-B, includes a dummy gate dielectric 2922 and adummy gate 2924, with a spacer 2926 extending along 2920′s sidewalls.However, the dummy gate structures 2900 and 2920 will not be replaced byactive gate structures at operations 1816 and 1818, for example, bymasking the dummy gate structure 2900 and 2920 at operations 1816 and1818. Upon the formation of the active gate structures 2702 and 2712,both of the active gate structures, 2702 and 2712, and the dummy gatestructures, 2900 and 2920, can be recessed so as to overlaid byrespective dielectric hard masks. For example, the dummy gate structures2900 and 2920 are overlaid dielectric hard masks 2908 and 2928,respectively.

FIG. 30 illustrates a cross-sectional view of another embodiment of thememory device 1200, which can be made based on the layout 900 of FIG. 9. Referring again to FIG. 9 , the layout 900 includes an additional gatefeature 908 (with respect to the layout 500 of FIG. 5 ) that travelsacross the active feature 902B, which results in forming the active gatestructure of another GAA transistor. For example in FIGS. 19A-C, afterforming an additional dummy gate structure (with respect to the dummygate structures 1902 and 1912) using the gate feature 908 at operation1802 of FIG. 18 , the rest of the operations of the method 1800 of FIG.18 can be used to form the memory device 1200, which includes onenon-GAA transistor and two GAA transistors.

As shown in FIG. 30 , in addition to the active gate structures of thenon-GAA transistor 2410 and the GAA transistor 2210, which can be formedby the gate features 904 and 906, respectively, the memory device 1200includes an active gate structure 3006 of another GAA transistor 3000,which can be formed by the gate feature 908. As the gate features 906and 908 both travel across the active feature 902B, the formed GAAtransistors 2210 and 3000 may share the source/drain structure 2204, buthave respective channels. For example, the GAA transistor 3000 includesemiconductor layers 3002 collectively functioning as its channel. TheGAA transistor 3000 includes the shared source/drain structure 2204connected to one end of the semiconductor layers 3002, and asource/drain structure 3004 connected to the opposite end of thesemiconductor layers 3002. The active gate structure 3006 and thesource/drain structure 3004 are connected by respective interconnectingstructures, 3008 and 3010, to enable operation of the memory device 1200including one non-GAA programming transistor and two GAA readingtransistors. For example, a WLR2 is connected to the active gatestructure 3006 of the GAA transistor 3000 through the interconnectingstructure 3008 (with a WLR 1 is connected to the active gate structureof the GAA transistor 2210) and a BL is connected to the source/drainstructure 3004 of the GAA transistor 3000 through the interconnectingstructure 3010.

FIG. 31 illustrates a cross-sectional view of another embodiment of thememory device 1200, which can be made based on the layout 1000 of FIG.10 . Referring again to FIG. 10 , the layout 1000 includes one or moreadditional features (e.g., 1002 and 1004) when compared to the layout900 of FIG. 9 . The features 1002 and 1004 can be configured to formdummy gate structures that will not be replaced by active gatestructures.

As shown in FIG. 31 , the memory device 1200 further includes dummy gatestructures 3100 and 3120, when compared to the embodiment shown in FIG.30 that is made based on the layout 900 of FIG. 9 . The dummy gatestructures 3100 and 3120 can be formed using the features 1002 and 1004(FIG. 10 ), respectively, at operation 1802 of FIG. 18 . For example inFIGS. 19A-C, the dummy gate structures may be formed concurrently withthe dummy gate structures 1902 and 1912 that will be replaced byrespective active gate structures at operations 1816 and 1818. Thus,each of the dummy gate structures 3100 and 3120 includes the similarconfiguration as the dummy gate structures 1902 and 1912 except that thedummy gate structures 3100 and 3120 are formed over the isolationstructures 1630 (e.g., not to overlay any active region).

For example, the dummy gate structure 3100, formed over the isolationstructure 1630 opposite the active region 1603B from the active region1603A, includes a dummy gate dielectric 3102 and a dummy gate 3104, witha spacer 3106 extending along 3100′s sidewalls; and the dummy gatestructure 3120, formed over the isolation structure 1630 between theactive regions 1603A-B, includes a dummy gate dielectric 3122 and adummy gate 3124, with a spacer 3126 extending along 3120′s sidewalls.However, the dummy gate structures 3100 and 3120 will not be replaced byactive gate structures at operation 1820, for example, by masking thedummy gate structure 3100 and 3120 at operation 1820. Upon the formationof the active gate structures 2702, 2712, and 3006, both of the activegate structures, 2702, 2712, and 3006, and the dummy gate structures,3100 and 3120, can be recessed so as to overlaid by respectivedielectric hard masks. For example, the dummy gate structures 3100 and3120 are overlaid dielectric hard masks 3108 and 3128, respectively.

FIG. 32 illustrates a cross-sectional view of another embodiment of thememory device 1200, which can be made based on the layout 800 of FIG. 8. Referring again to FIG. 8 , the layout 800 includes the active feature802A partially overlaid by the gate feature 504 (with respect to thelayouts 500-700 of FIGS. 5-7 ), which results in forming a non-GAAtransistor having only one source/drain structure (a MOS capacitor). Forexample in FIGS. 19A-C, after forming the active structure 1602A usingthe active feature 802A at operation 1110 of FIG. 11 (or operation 1712of FIG. 17 ) and then forming the dummy gate structure 1902 using thegate feature 504 at operation 1802 of FIG. 18 , the dummy gate structure1902 can not only straddle the active structure 1602A but also extendalong one of the sidewalls of the active structure 1602A along the Xdirection. the rest of the operations of the method 1800 of FIG. 18 canbe used to form the memory device 1200, which includes one non-GAAtransistor, formed as a MOS capacitor, and one GAA transistor.

As shown in FIG. 32 , the memory device 1200 includes a non-GAAtransistor 3200, formed as a MOS capacitor. The non-GAA transistor 3200includes an active gate structure 3202, which replaces the dummy gatestructure 1902 formed by the gate feature 504 as described above. Theactive gate structure 3202, including a gate dielectric 3204 and a gatemetal 3206, not only straddles the active structure 1602A but alsoextend along one of the sidewalls of the active structure 1602A alongthe X direction. Respective sidewalls of the active gate structure 3202(along the X direction) are also overlaid by a gate spacer 3208. Assuch, the non-GAA transistor 3200 may only include the source/drainstructure 2404 formed along one of the sidewalls of the active structure1602A (along the X direction) that is not overlaid by the active gatestructure 3202.

In one aspect of the present disclosure, a memory device is disclosed.The memory device includes a first transistor formed in a first regionof a substrate. The first transistor includes a structure protrudingfrom the substrate, and a first source/drain (S/D) structure coupled toa first end of the protruding structure. The memory device includes asecond transistor formed in a second region of the substrate. The secondtransistor includes a number of first semiconductor layers that arevertically spaced apart from one another, a second S/D structure coupledto a first end of the first semiconductor layers; and a third S/Dstructure coupled to a second end of the first semiconductor layers. Thefirst region and the second region are laterally separated from eachother by an isolation structure.

In another aspect of the present disclosure, a one-time-programmable(OTP) memory device is disclosed. The OTP memory device includes aprogramming transistor formed in a first region of a substrate. The OTPmemory device includes a first reading transistor electrically coupledto the programming transistor in series and formed in a second region ofthe substrate. The first region is laterally separated from the secondregion by an isolation structure. The programming transistor includes afirst gate structure straddling a structure protruding from thesubstrate, and the first reading transistor includes a second gatestructure wrapping around each of a plurality of first nanostructuresthat are vertically spaced apart from one another.

In yet another aspect of the present disclosure, a method forfabricating a memory device is disclosed. The method includes defining afirst active region and a second active region over a substrate. Thefirst and second active regions are laterally spaced apart from eachother by an isolation structure. The method includes forming a firsttransistor in the first active region. The first transistor includes afirst channel formed of a structure protruding from the substrate, afirst active gate structure straddling over the first channel, and atleast a first source/drain structure coupled to one end of the firstchannel. The method includes forming a second transistor in the secondactive region. The second transistor includes a second channelcollectively formed of one or more semiconductor layers disposed overthe substrate, a second active gate structure wrapping around the secondchannel, a second source/drain structure coupled to one end of thesecond channel, and a third source/drain structure coupled to the otherend of the second channel.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A one-time-programmable (OTP) memory device,comprising: a programming transistor formed in a first region of asubstrate; and a first reading transistor electrically coupled to theprogramming transistor in series and formed in a second region of thesubstrate, the first region being laterally separated from the secondregion by an isolation structure, wherein the programming transistorincludes a first gate structure straddling a structure protruding fromthe substrate, and the first reading transistor includes a second gatestructure wrapping around each of a plurality of first nanostructuresthat are vertically spaced apart from one another.
 2. The OTP memorydevice of claim 1, wherein the protruding structure is configured as achannel of the programming transistor, and the plurality ofnanostructures are collectively configured as a channel of the firstreading transistor.
 3. The OTP memory device of claim 1, wherein theprogramming transistor includes a first source/drain (S/D) structurecoupled to a first end of the protruded structure, and the first readingtransistor includes a second S/D structure and a third S/D structurescoupled to a first end and a second end of the plurality of firstnanostructures, respectively.
 4. The OTP memory device of claim 3,wherein the first S/D structure and the second S/D structure areimmediately adjacent to but separated from each other by the isolationstructure.
 5. The OTP memory device of claim 3, wherein the first S/Dstructure has a first vertical height, and the second S/D structure andthird S/D structure have a second vertical height, the second verticalheight being greater than the first vertical height.
 6. The OTP memorydevice of claim 3, further comprising an interconnecting structure thatis disposed above the substrate and connects the first S/D structure toat least one of the second S/D structure or the third S/D structure. 7.The OTP memory device of claim 1, further comprising a second readingtransistor electrically coupled to the first reading transistor inseries and formed in the second region of the substrate, wherein thesecond reading transistor includes a third gate structure wrappingaround each of a plurality of second nanostructures that are verticallyspaced apart from one another.
 8. The OTP memory device of claim 1,further comprising at least one dummy gate structure disposed betweenthe first region and the second region.
 9. A memory device, comprising:a substrate including a first region and a second region, wherein thefirst region and the second region are separated from each other with anisolation structure; a first transistor formed in the first region; anda second transistor formed in the second region and coupled to the firsttransistor in series through an interconnecting structure, wherein thefirst transistor includes a first gate structure straddling a structureprotruding from the substrate, and the second transistor includes asecond gate structure wrapping around each of a plurality of firstnanostructures that are vertically spaced apart from one another. 10.The memory device of claim 9, wherein the first transistor and thesecond transistor collectively serve as a one-time-programmable (OTP)memory cell.
 11. The memory device of claim 9, wherein the protrudingstructure is configured as a channel of the first transistor, and theplurality of nanostructures are collectively configured as a channel ofthe second transistor.
 12. The memory device of claim 9, wherein thefirst transistor includes a first source/drain (S/D) structure coupledto a first end of the protruded structure, and the second transistorincludes a second S/D structure and a third S/D structures coupled to afirst end and a second end of the plurality of first nanostructures,respectively.
 13. The memory device of claim 12, wherein the first S/Dstructure and the second S/D structure are immediately adjacent to butseparated from each other by the isolation structure.
 14. The memorydevice of claim 12, wherein the first S/D structure has a first verticalheight, and the second S/D structure and third S/D structure have asecond vertical height, the second vertical height being greater thanthe first vertical height.
 15. The memory device of claim 12, whereinthe connecting structure connects the first S/D structure to one of thesecond S/D structure or the third S/D structure.
 16. The memory deviceof claim 9, further comprising a third transistor electrically coupledto the second transistor in series and formed in the second region ofthe substrate, wherein the third transistor includes a third gatestructure wrapping around each of a plurality of second nanostructuresthat are vertically spaced apart from one another.
 17. The memory deviceof claim 9, further comprising at least one dummy gate structuredisposed between the first region and the second region.
 18. A memorydevice, comprising: a substrate including a first region and a secondregion, wherein the first region and the second region are separatedfrom each other with an isolation structure; a first transistor formedin the first region and comprising: a first gate structure straddling astructure protruding from the substrate; a first source/drain (S/D)structure coupled to a first end of the protruded structure; and asecond transistor formed in the second region, coupled to the firsttransistor in series through an interconnecting structure, andcomprising: a second gate structure wrapping around each of a pluralityof first nanostructures that are vertically spaced apart from oneanother; a second S/D structure coupled to a first end of the pluralityof first nanostructures; and a third S/D structure coupled to a secondend of the plurality of first nanostructures.
 19. The memory device ofclaim 18, wherein the first S/D structure has a first vertical height,and the second S/D structure and third S/D structure have a secondvertical height, the second vertical height being greater than the firstvertical height.
 20. The memory device of claim 18, wherein theconnecting structure connects the first S/D structure to one of thesecond S/D structure or the third S/D structure.